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Computer Organization and Architecture II

Computer Organization and Architecture II. Important Dates. Midterm Exam II: 3/6 Midterm Exam III: 4/17 Final Exam: 5/9 Spring Break (3/8-3/16). Data Bus. 12657. …. input/ output. Load x. memory. Load x. 12657. …. control unit. Central Processing Unit (CPU).

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Computer Organization and Architecture II

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  1. Computer Organization and Architecture II

  2. Important Dates • Midterm Exam II: 3/6 • Midterm Exam III: 4/17 • Final Exam: 5/9 • Spring Break (3/8-3/16)

  3. Data Bus 12657 … input/ output Load x memory Load x 12657 … control unit Central Processing Unit (CPU) The PC (Program Counter) register contains the memory address of the next instruction to execute. registers program counter PC instruction register IR computation register R arithmetic- logic unit That instruction is loaded into the IR (Instruction Register). condition flags: GT, EQ, LT The Organization of a von Neumann Computer • Recall von Neumann’s key insight: • computers can be programmed with software • programs can be stored as data in memory

  4. The Simplicity of a von Neumann Machine assuming that PC has an initial value The CPU executes one program, looping indefinitely: 1. Fetch from memory: Set IR to contents of PC Increment PC 2. (Decode and) Execute: (decompose IR into operation and operands) apply the operation to the operands 3. Go To 1 Let’s postpone discussing the Decode step until the end of the lecture

  5. Instruction Set (from figure 5.19) Operation Meaning • Load X Con(X)  R • Store X R  Con(X) • Clear X 0  Con(X) • Add X R+Con(X)  R • Increment X Con(X)+1  Con(X) • Subtract X R-Con(X)  R • Decrement X Con(X)-1  Con(X) • Compare X if Con(X)>R then GT=1 else 0 • if Con(X)=R then EQ=1 else 0 • if Con(X)<R then LT=1 else 0 • Jump X get next instruction from location X • JumpGT X Jump X if GT=1 • JumpEQ X Jump X if EQ=1 • JumpLT X Jump X if LT=1 • In X input an integer value and store in X • Out X output the value in X • Halt halt execution

  6. Data Bus contents address Control Unit 10 Load X 11 Add Y 12 Store Z 13 Jump Nxt 14 Subtract X 15 Clear X ........... 20 7 21 4 22 0 23 0 instruction pointer PC instruction register IR computation register R instructions (Nxt) condition flags (X) (Y) (Z) (CN1) data Arithmetic-Logic Unit CPU Memory Example of fetch-execute cycle the memory cells actually contain binary numbers ... more on this later

  7. Data Bus contents address Control Unit 10 Load X 11 Add Y 12 Store Z 13 Jump Nxt 14 Subtract X 15 Clear X ........... 20 7 21 4 22 0 23 0 instruction pointer PC instruction register IR computation register R instructions 11 Load X (Nxt) condition flags (X) (Y) (Z) (CN1) data Arithmetic-Logic Unit CPU Memory step 0: to execute the program, initialize PC to 10 step 1:fetch instruction & increment PC 10

  8. Data Bus contents address Control Unit 10 Load X 11 Add Y 12 Store Z 13 Jump Nxt 14 Subtract X 15 Clear X ........... 20 7 21 4 22 0 23 0 instruction pointer PC instruction register IR computation register R instructions (Nxt) 7 condition flags (X) (Y) (Z) (CN1) data Arithmetic-Logic Unit CPU Memory Step 2: (Decode and) Execute Step 3: Go To Step 1 11 Load X

  9. Data Bus contents address Control Unit 10 Load X 11 Add Y 12 Store Z 13 Jump Nxt 14 Subtract X 15 Clear X ........... 20 7 21 4 22 0 23 0 instruction pointer PC instruction register IR computation register R instructions 12 Add Y (Nxt) condition flags (X) (Y) (Z) (CN1) data Arithmetic-Logic Unit CPU Memory step 1:fetch instruction & increment PC 11

  10. Data Bus contents address Control Unit 10 Load X 11 Add Y 12 Store Z 13 Jump Nxt 14 Subtract X 15 Clear X ........... 20 7 21 4 22 0 23 0 instruction pointer PC instruction register IR computation register R instructions 12 Add Y (Nxt) 7 11 condition flags (X) (Y) (Z) (CN1) data Arithmetic-Logic Unit CPU Memory Step 2: (Decode and) Execute Step 3: Go To Step 1 and so on, and so on ...

  11. bit # 0 1 2 3 4 15 memory cell Decoding each instruction • Instructions in memory are represented with binary numbers. • In our hypothetical computer, they might be encoded as: instruction code: 24 = 16 possible codes memory address: 212 = 4,096 memory locations can be addressed • The decoder’s job is to pick out the instruction code and the memory address from the binary number in the memory cell. To the decoder, instructions are data!

  12. Programming – Exercise • Print the sum of two numbers input by the user • Input a number, then compute and print its absolute value • Let’s try it

  13. Programming – Exercise • Write factorial program: 4! = 4*3*2*1. The algorithm looks like: The user inputs num. Set product to 1. While (num > 0) product is product * num. num is num –1. STOP

  14. Summary • Every conventional computer is based on the von Neumann architecture • von Neumann’s key insight was that computers could be instructed with software, and that instructions could be stored in memory • Computers execute programs using the fetch-(decode)-execute cycle • Because of its simplicity, engineers have built increasingly fast hardware to implement the cycle

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