A Brief Overview of Make

1. A Brief Overview of Make Brandon Packard

2. Why make? • So far, you have probably worked on relatively small projects • Coding projects can become huge • My research consists of 1600 java files (not all written by me of course)

3. Are makefiles worth it? • Imagine typing out javac file1.java, file2.java, file3.java, …., file1600.java • Could store the compilation command in a text file, but there is an easier way

4. What is make? • Make is a tool that lets you compile code with a single small command. • Implemented on tux, with the “make” command. • Requires a Makefile to work

5. Writing a Makefile • 4 major pieces (for our purposes): • Variables • Targets • Commands • Prerequisites

6. Variables • Declared at the top of the file • Much like variables in bash • CC = g++ • Now you can use $(CC) instead of g++

7. Variables • Variables can be set to represent an entire group of files • Can make the main body of the make file much easier to read.

8. Targets • These are what you reference from the command line • For makefiles that can do multiple things, this lets you specify which behaviour you want • Syntax is the name of the target followed by a colon.

9. Target examples • clean: • run: • To run the clean target, you would type “make clean” at the command line. • Default target is the first one in the file.

10. Commands • These are what get executed when you run make. • Go on the line under the target • Can compile code, run files, clean up directories, mostly anything you can do in the shell

11. Example Commands • $(CC) -c markov.cpp • Compiles the code but does not link it • rm -f *.o • Removes all object files from the current directory • $(someProgram) > $(someFile) • Runs the program in the first variable and puts the output to the file held as the second variable

12. Prerequisites • Used to the commands have the files they need • Can also be used to order targets • If the prerequisite is empty, another target may be ran to obtain it

13. Prerequisites • Are placed on the same line as the target, after the colon: • run: someJavaFile.class • If the class file is not present, make will try to obtain it by running other targets (such as a compile target)

14. A (fairly) simple make file RESULT=hello all: $(RESULT) $(RESULT): main.o g++ main.o -o $(RESULT) main.o: main.cpp g++ -c main.cpp clean: rm -rf *o $(RESULT)

15. A (fairly) simple make file RESULT=hello all: $(RESULT) $(RESULT): main.o g++ main.o -o $(RESULT) main.o: main.cpp g++ -c main.cpp clean: rm -rf *o $(RESULT) Variable Target Prerequisite Command

16. A (fairly) simple make file RESULT=hello all: $(RESULT) $(RESULT): main.o g++ main.o -o $(RESULT) main.o: main.cpp g++ -c main.cpp clean: rm -rf *o $(RESULT) 1. all target calls the RESULT target 2. RESULT needs main.o, but does not have it. Calls main.o target Command: make all (assume we only have main.cpp)

17. A (fairly) simple make file RESULT=hello all: $(RESULT) $(RESULT): main.o g++ main.o -o $(RESULT) main.o: main.cpp g++ -c main.cpp clean: rm -rf *o $(RESULT) 4. RESULT now has its prerequisites fulfilled - links object file into executable 3. main.o target runs this command to compile (but not link) main.cpp Command: make all (assume we only have main.cpp)

18. A (fairly) simple make file RESULT=hello all: $(RESULT) $(RESULT): main.o g++ main.o -o $(RESULT) main.o: main.cpp g++ -c main.cpp clean: rm -rf *o $(RESULT) command: make clean the clean target will remove all of the object files in the directory, as well as the executable

19. Makefiles can be very complex • Makefiles can be full of special targets, implicit rules, and even conditionals • Simple makefiles should suit our purposes well enough • Will be using make files to submit your other programming assignments

20. Fin • Questions? • Comments? • Concerns? • Doubts about my sanity?