Verification of embedded system specifications using collaborative simulation of SysML and Simulink models

1. Verification of embedded system specificationsusing collaborative simulation of SysML and Simulink models Ryo Kawahara*, Hiroaki Nakamura*, Dolev Dotan**, Andrei Kirshin**, Takashi Sakairi*, Shinichi Hirose*, Kohichi Ono*, Hiroshi Ishikawa* *Tokyo Research Laboratory, IBM Research **Haifa Research Laboratory, IBM Research

2. Abstract • The authors propose an extension of SysML which enables description of continuous-time behavior. • The authors also develop its execution tool integrated on Eclipse-based platform by exploiting co-simulation of SysML and MATLAB / Simulink. • To demonstrate the effectiveness of the tool and the extension to SysML in verifying specifications of an embedded system, we create a sample model and analyze its execution results by checking constraints under a test case.

3. Introduction • In the development of an embedded system, it is important to verify that the specification of the system satisfies the requirements at an early stage • One approach to achieve this is to model and simulate the system during the analysis • Systems Modeling Language (SysML) is an extension of UML for embedded systems to include heterogeneous elements such as software, electronics, or mechanics

4. Subject • Embedded systems often include control systems • A control system is usually a hybrid system, the mixture of continuous-time and discrete behavior • Continuous-time behavior in UML / SysML has not been defined • Simulation of control system is usually done in a specialized tools, such as the MathWorks MATLAB / Simulink • A UML / SysML behavior is not associated with time • Integration of the continuous-time behavior into the systems model is desired

5. Background: SysML • SysML is an extension of UML2 for systems engineering

6. Background: Simulink • Simulink uses Block diagram • Block diagram describes the flow of signal between blocks, which process the signal • This example calculates:

7. Approach • Use SysML for a system architecture description • Use specific languages for each domain • Simulink for continuous-time behavior in a control system • Time duration assignment to SysML action • Verify specification by collaborative simulation • Run multiple simulation in parallel with time synchronization • Independent time management module

8. Extended Modeling for Simulation in SysML

9. Running Transition Execution Pending Current State Breakpoint SysML Execution and Debugging • Debugging of behavioral UML models by emulation, supporting: • Class, Composite Structure Diagrams • State Machines, Activities • Java as Action Language • Extensible to support UML profiles (in this case SysML) • Debugging UI – Model Debugging Perspective (next slide) • Diagram animation • Debugging modes: • Traditional Debugging • Start “main” • Run to breakpoint • Stepping • Interactive debugging(model “exerciser”) • Manually create objects • Invoke operations • Send signals

10. Model Debugging Perspective Sleeping Breakpoints Debug Variables Event Pools Watch Diagram Animation Instances Signals Console Snippet I/O

11. Sleeping View Shows the queue of sleeping behaviors and behavior elements. Current virtual time Wakeup time

12. Time Management • Data is exchanged and the next Simulink step is executed at: • End of timed SysML behavioral step (<<GaStep>> or sleep()) • Periodic data exchange event Discrete events SysMLobject SysMLobject SysMLobject MATLAB / Simulink Action3 … Action2 Action1 Demands of time Simulation start / stop Add periodic data exchange events into the list consists of the discrete events MATLAB / Simulink command execution Periodic data exchange events Time demands to scheduler Time management module Time Timed scheduler 0 100 200 300 400 UML execution engine

13. Temporary generated Simulink model Input S-Function Model reference1 Model reference2 OutputS-Function Data from SysML Data to SysML Model 1 Model 2 Simulink models which are assigned to SysML behaviors Co-simulation with Simulink • All the Simulink models are referred from a single temporary Simulink model • Only one Simulink process is used • Simulation data is sent or received through Input/Output S-Functions

14. Overview of Sample model: Humidifier • Requirements • The humidifier starts vapor emission within 5 minutes since the power on signal • The humidifier ends cool down within 10 minutes since the power off signal • The humidifier keeps the room humidity at a constant level specified by the user automatically • Basic mechanism • The water is boiled by the heater • Vapor is emitted to the environment by circulator fan Circulator fan Reservoir Pan Heater

15. Structure of HumidifierSystem Block definition diagram Internal block diagram of HumidifierSystem Flow ports for continuous I/O Simulink model assigned block Standard ports for discrete signals State machine assigned block Simulink model assigned block State machine assigned block

16. Behavior of Control block State machine diagram Signal from user interface Change event that monitors values from a Simulink blocks

17. Simulink model for VaporGenerationPlant heating subsystem radiation subsystem evaporation subsystem

18. Test context Block definition diagram Internal block diagram of TestContext Definition of test environment Flow ports for continuous I/O to consist a closed loop Simulink model assigned block Test target

19. Test case and results Cooling down taking too long time Automatic humidity control

20. Parametric and time constraint evaluation Sequence diagram with time constraint using MARTE profile Parametric diagram Constraint block: Humidity should be kept near target value Timed constraint: Cool down should be finished within 10 minutes

21. Conclusion • We have developed a verification tool based on co-simulation of Simulink and SysML • We have extended the modeling capability of SysML to be able to reference Simulink models and specify timed behavior • These extensions enable one to test specifications of a system which includes continuous-time behavior in a closed control loop

23. Block2 Block3 Integer b = 1 Integer c = 2 <x,y,z> {a,b,c} |{d,e,(f|g}} {h,i} p q p q {n,o} {j,k} l m Overview of the verification tool TPTP-based test driver Time-aware UML execution engine Simulink Timed test cases Timed discrete behavior Continuous behavior Virtual time scheduler Binary tree for fast eval. Eval > 80 Parametric constraints (OMG SysML) Time constraints (OMG MARTE profile) eval Integer eval eval eval = f(bb, cc) bb cc Parametric constraint evaluator Time constraint evaluator

24. Simulink model for Room block relative_humidity subsystem saturation_vapor_pressure subsystem

25. State machine diagram of HeaterControl block

26. Related works Studies on coupling of UML/SysML and continuous-time simulation (e.g., Simulink)

27. Related works • Source code level linkage of UML and Simulink • Reichmann et al., 2004. Telelogic Rhapsody® • Co-simulation of Simulink and UML model on IBM Rational Rose® RealTime • J. Hooman, N. Mulyar and L. Posta, 2004 • Conversion of UML/SysML to Modelica language • C. Nytsch-Geusen, 2007. A. Pop et al., 2007. T. A. Johnson et al., 2008 • Modelica is a new language to model continuous-time system