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SVA assignment

SVA assignment. (System Verilog Assertion). Assignment Guideline. You need do Assertion Labs on Unix Platform Require to have an account @EE231.NTU Login-in machine (Recommended) cad32.ee.ntu.edu.tw or 140.112.20.75 (Solaris 8) Add one line command in your .cshrc

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SVA assignment

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  1. SVA assignment (System Verilog Assertion)

  2. Assignment Guideline • You need do Assertion Labs on Unix Platform • Require to have an account @EE231.NTU • Login-in machine • (Recommended) cad32.ee.ntu.edu.tw or 140.112.20.75 (Solaris 8) • Add one line command in your .cshrc • source /usr/cad/synopsys/CIC/vcs_sv.csh • You can verify environment setting by the instruction “vcs –help”. If no error message, your working environment is O.K. • Copy material from course web-site • SVA_training.pdf • Detail lab descriptions • Lab source code

  3. Assignment Guideline • What do you need to do ?? • Basic Requirements • Revise “traffic.v” file for lab1. • Revise “.sv” files in lab2 to lab4. You need to complete the assertions. • If there is any error report, fix the original “.v” files and rerun the assertions. • What to turn in? • Revised “.v” or “.sv” files • “assertion.report” files from VCS • Simple README file to explain what you do for each lab • Bonus • Answer “Questions” at the end of each lab in SVA_training.pdf

  4. Assignment Guideline • References • ova_checkerlib_ref.pdf (1.2MB) • sva_checkerlib.pdf (2.4MB) • dve_ug.pdf (3.7MB) • vcs.pdf (12MB)

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