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Designing of a D Flip-Flop Final Project ECE 491

Designing of a D Flip-Flop Final Project ECE 491. Objectives. To familiarize with the function of the D flip- flop and it's operation. To Draw the schematic and the layout with clocked input Perform DRC check and generate LVS To do the simulation and observed the output waveforms

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Designing of a D Flip-Flop Final Project ECE 491

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  1. Designing of a D Flip-FlopFinal ProjectECE 491

  2. Objectives • To familiarize with the function of the D flip- flop and it's operation. • To Draw the schematic and the layout with clocked input • Perform DRC check and generate LVS • To do the simulation and observed the output waveforms • To Vary the output load(1pf to 5pf) and observed outputs

  3. D Flip Flop (Specification) • A signal input and a clock signal is used • AMI-0.6micron process is used • Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u • Pre and Post-layout simulations using spectra • Rise time, Fall time and propagation delay increase for the loading effects

  4. Why DFF • Preferred type for integrated circuit applications (DFF) • S-R flip flop has indeterminate state when both inputs are high • The JKFF simplifies the RSFF truth table but keeps two inputs.

  5. Symbol CLK Q DFF D QB

  6. Layout

  7. Schematics Q QB Inverter Nor And And Nor

  8. INVERTER NAND NOR AND

  9. Results

  10. Delay

  11. Without load

  12. Loading Effect

  13. Negative Edged Trigger

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