Frequency and Time Synthesis A Tutorial Victor S. Reinhardt June 6, 2000. Frequency and Time Synthesis Tutorial Organization. Basic Concepts What is a Synthesizer? Basic Concepts of Frequency and Time Synthesis Direct Analog Synthesis Analog Building Blocks
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One or More
Reference Sources
fr1
Synthesizer
.
.
.
Output fo
frN
attn=nTo
n=2n
V
Amplitude A
t
Sine Wave
Period To
=2
V
Amplitude A
t
Pulse
Ideal Periodic WaveformV = A F(F)
F = Phase of Function
F(F + 2) = F(F)
wo=Angular Frequency
wo= 2pfo
fo = 1/To = Frequency
w = df/dt
f =w/2p
y = w/wo = df/foy = (df/dt) / wo
V
Peak VariationAmplitude Error
t
Zero Crossing VariationTime or Phase Error
V = ( A + a(t) )·F[ wot + f(t) ]
a(t) Amplitude Error
f(t) Phase Error
Near ZeroV = A(wot+f(t))
V
F, t
dV
f, dt
Additive Noise and Phase & Time Errorf(t) = dV(t)/A
dt = f/wo = dV/(Awo)
For NonSine Wave: Effective A is Determined by Slope Near Zero
Complex Representation
dVQ
f
A
dVI
dVI = dVQ = dV
Basic Clock
fo
Frequency
Reference
Cycle
Counter
x
x
dt
Ideal Source
dwo
Kdwr
dwr
yo =
=
=
=
yr
wo
Kwr
wr
fo
Kfr
fr
xo =
=
=
=
xr
wo
Kwr
wr
Ideal Coherent Synthesizerfr
fo= Kfr
Ideal
Coherent
Synthesizer
fr
fo= Kfr
Frequency
Reference
Filter
H(f)
V(f) = H(f)U(f)
U(f)
Sv(f) = H(f)2Su(f)
dx
y(t) =
dt
df
y(t) = wo1
dt
w2
Sy(f) = Sf(f)
wo2
Spectral Density ReviewSy(f) = w2Sx(f)
Phasor Diagram
2pDf
Vo(t)
Spur at
fo+Df
wo
f
x
Discrete Samples When Phasor Crosses Real Axis
Phase Error Plot
s(t)
Allan Variance
Counter Histogram
t
Noise
fa
fa fb
fb
f
f
Switches
f1
fin
f2
fo
x
fout
x
.
.
.
.
fn
Direct Analog SynthesisMultipliers
x N
f
Nf
f
Nf
Dividers
f
f/M
÷ M
f
f/M
x
x
Filters
fb
fa+fb+fc
f
f
Amplifiers
x
x
f2
f3
f1
Switch
Matrix
...
9fr
2fr
fr
Reference
Generator
fr
Typical Direct Analog Synthesizer: Divide & Mixfo = f1+ f2/10+f3/100
fo = [N1+ N2/10+N3/100 + …]fr
fk=Nkfr
(Nk = 0 to 9)
f1=N1fr
+ 10
f2+f3/10
f2=N2fr
f3/10
+ 10
f3=N3fr
1/f
Noise
White Noise
Floor
1/f Knee
f
Si 110 KHz
GaAs, InP 0.11 MHz
1/f Knees
Component Design ParametersPhase Noise Characterization of Devices
Cascaded Multipliers & Dividers
xN1
xN2
xN3
÷N3
÷N2
÷N1
FF
FF
...
FF
fin
fout
Cleanup Circuit
fin
f’out
fout
One
Shot
Synchronous Counter
...
fout
fin
FF
FF
FF
Regenerative
Delayt Divider
Set
RS
FF
Q
fin
fout
Delay
t
Reset
Frequency Dividers (Counters)Modulus
Counter
÷ P/P+1
fin
÷
Out
P/P+1
Control
÷A
Reset
A
Counter
Reset
M
Counter
÷M
fout
Dual Modulus Counterf
Nf
Nonlinear
Device
Filter
Sharpness of DistortionFeatures (t) Determine Amplitude ofHigh Harmonics
Good Efficiency Limit Nf 1/t
Device Degradation Due to Overdrive
fR
fLO
fIF
Harmonics of fLO
Harmonics of fR
IF to Spur Ratios (dB)
Mixers(WJM9E)
Filter
fo = T1(fr)
VCO
Freq
Control
Frequency
Translation
Error
Signal
Phase or
Frequency
Discriminator
T(fo)
fr
Indirect Synthesis
fo = Nxfr
Loop
Filter
VCO
÷N
Error
Signal
fo/N
fr
Example: Divider Loop
Indirect Synthesisf = fo Vo/s
Vi = fr f
VCO
fr
f
f
Vi
G(f)
Vo
Vo = G(f) Vi
H(f)
1H(f)
1
1
f
f
fn
fn
Basic Phase Locked LoopH(f) = f/fr = G(f)/(s + G(f))
f = H(f)fr + (1H(f))fo
Idealized PLL
Sf(f)
Free Running VCO Sf(f)
Reference Sf(f)
Optimum
PLL Sf(f)
f
Optimum fn
Optimum Loop BandwidthLoss = L
Resonator
fR = fa= 2QL·y
Sy(f)= 1/(2QL)2Sa(f)
Sf(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Loaded Q = QL
Near Resonance
fR = 2QL·y
Oscillation Conditions
GaL = Loop Gain > 1
Sf Around Loop = 0
Pin
Amp
Gain = Ga
Noise Figure = F
Flicker Knee = ff
Noise Density = FkT
Converted Noise + Original Amp Noise
Sf(f)
K3/f3
Converted Noise
QL
K2/f2
Amp Noise
K1/f
K0
f
Oscillator Noise SpectrumOscillator Noise Spectrum
Leeson’s Equation
Sf(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Sf(f)
xN
Nfo
fo
N2
N2
f
Sf(f) = N2(fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Oscillator at fovs Nfo(Same QL)
Sf(f)
vs
fo
Nfo
N2
Sf(f) = (Nfo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Multiplied Oscillator vs Higher Oscillator Frequencyz =
wn
2szwn+wn2
H =
H =
s + wn
s2+2szwn+wn2
1st & 2nd Order PLLs1st Order PLL
2nd Order PLL
fr
f
fr
f
VCO
VCO
wn = G
1H = s for s << wn
1H = s2 for s << wn
fo
VCO
Analog
Loop
Filter
Analog Frequency
Translation
Voltage Output
Phase Detector
fr
Divider Loop
fo/N
fo
fr
÷N
Multiplier Loop
frxN
fo
fr
xN
fr1
.
.
frk
Digital (Loop Filter) PLLsDigital
Loop
Filter
fo
VCO
D/A
Analog
Down
Conversions
Averaging
..
fIF1
fIFk
Digital
Frequency
Translations
Counters
fc from VCO
TIF = 1/fIF
tnk
Tc = 1/fc
fIFk = 2p ( n  fIFk tnk )
df = 2p Tc / TIF = 2p fIF / fc
VCXO
VCXO
AFS
fo
fo
fr1
fIF1
Down
Converter
AFS
1
D/A
3.17 MHz
13.4 MHz
AFS’s
100 Hz
4
Event Clock
& PLL Processor
fr2
Down
Converter
AFS
2
180 KHz
fIF2
76
Event Clock &
PLL Processor
3.53 KHz Cs
2.76 KHz Rb
10.23 MHz
from VCXO
98 ns
Event Clock
From D/C
x 2n
N
+
+
2nd Order
Loop Filter
To D/A
N= 3800 Cs
N= 4858 Rb


Compute
Phase
Integrate
x n2/s
~100 Hz
Integrate
Downconverter
f Offset
f Offset
Example of Digital PLL(Reinhardt, 1999)
Pong
Switch
fo
2nd
PLL
Pre
tune
÷N
Adaptive
Loop
Filter
fr
Pre
Charge
Reclock
& Clear
Divider
Fast Settling Loop TechniquesLoop TC = 0.1 s
(Reinhardt, 1999)
Mechanical Model of PLL with Noise
Noise Burst
Causes
Cycle
Slip
Average Noise
Energy
f
(Kroupa, 1973)
Response to Voltage Step
PostTuning Drift
VCO Frequuency
Single
Exponential
Equivalent Circuit of a Diffusion Process
Carry
Carry
Timing
Jitter
Carry
Clock
Cycles
Tc
1
2
3
4
5
6
7
8
9
Pulse
Out
Pulse Output DDSAccumulator Used as DDS
Rin + K Rout in Nbit arithmetic
fo
Frequency
Word K
Pulse Out
NBit
Adder
A
Carry
NBit
Register
Rout
B
A+B
fc
Rin
“Square”
Wave Out
MSB
Clock
f
=
0
.
1
2
2
5
H
z
f
=
1
H
z
o
c
0
Carrier
20
40
60
80
0
0.2
0.4
0.6
0.8
1.0
F
r
e
q
u
e
n
c
y
(
H
z
)
Bits
fc
Sine
Table
NBit
Accumulator
K
JBits
fo
Filter
DAC
MBits
Sine Output DDSStepped DDS Output
11Bit DAC
0
10
20
30
40
50
60
70
80
90
dBc
fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
Typical Sine Output DDSFrequency SpectrumsSTEL2373,[1]
Raytheon [2]
19
Plessey(4) SP2002,[3]
29
Rockwell,[4]
39
TI / Lincon Labs LDDS,[5]
Sciteq DCP1A,[7]
49
Sciteq ADS43x[7]
59
Sciteq (5) ADS63x [7]
69
Hughes Space[8],[9]
79
Philips Microwave
Limeil,Thomson CNI[10]
25
125
333
190
245
295
450
TRW DDS/HDAC1,[11]
0.29
DAC Triquent SC0806
C,(1)[21]
High Speed DACsSpur Levels vs SpeeddBc
Output Frequency (MHz)
(Essenwanger & Reinhardt, 1998)
214x12
1:1
(none)
97.23
Modified
28x9
Unmodified
Sunderland
28x11
12bits
±2 LSB
59:1
51:1
adder
adder
86.91
Sunderland
28x4
28x4
28x9
Nicholas
128:1
adder/subtract
88.94
28x3
27x14
Conventional
Taylor Series
2 adders
multiplier
64:1
97.04
27x9
25x3
14 pipelined stages
18 Bits Wide
Cordic
(none)
N/A
84.25
27x14
Raytheon
Taylor
Series
multiplier
multiplexer,
adder
13bits
±1 LSB
27x11
67:1
25x7
3 pipelined stages
Requires 1 calc
of Sinf & Cosf per Freq
IIR Filter*
(Presti, et. Al.)
(none)
N/A
No Limit
Sine Table CompressionAlgorithmsCompression
Algorithm
ROM
Req’ed
Compression
Ratio
Logic
Circuits
Algorithm
Error (dBc)
(*Modified from Essenwanger & Reinhardt, 1998)
Carry
Carry
Clock
Cycles
Fractional Divider or Pulse Swallowing DDSR + K R
fc
fo
K
Dual
Modulus
Prescaler
÷n/n+1
NBit
Accumulator
Carry
÷n/n+1
Control
fr
Linear
Phase
Detector
K
R
DAC
NBit
Accumulator
Loop
Amp
Carry
Output
n/n+1
Control
fo
VCO
Divide by
n/n+1
Phase Interpolation Fractional Divider (in PLL)Accumulator
Samples v(r)
at rn=fotn
Stepped
Output
Hold Function
LookUp
Table
v(r)
tSpace Sampled
Spectrum
Output Spectrum
rSpace Spectrum
Harmonics
1
1
3
3
5
5
7
7
1
3
5
7
rSpace Frequency
0
0
fo
2fc
fc
2fc
kfc/b = 0, fc/b, 2 fc /b, …. (b1) fc /b, ....
kfc/b = mfo  m’fc = [m(a/b)  m’]fc
r + p
v(r + p)
NBit
Accumulator
v(r)
Random
Number
Generator
Fractional
Frequency F
p
Destroying Coherence With Register JitterHeuristic Explanation
Spur Height Reduced Because of Larger Jitter
S(f)
Jitters
Output at fo
by
Jitters spur from mth Harmonic of v(r) by m
fo
fspur
f
Converts Spurs to Broadband Spectrum
f
=
0
.
1
2
2
5
H
z
f
=
1
H
z
f
=
0
.
1
2
2
5
H
z
f
=
1
H
z
o
o
c
c
0
0
Carrier
Carrier
20
20
40
40
60
60
80
80
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
F
r
e
q
u
e
n
c
y
(
H
z
)
Without Jitter Injection
With Jitter Injection
0
10
10
20
20
30
30
40
40
50
50
60
60
70
70
80
80
90
90
dBc
dBc
Randomized DAC DDS Experimental Results5Bit DAC No Jitter
5Bit DAC With Jitter
11Bit DAC No Jitter
fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
(Reinhardt,1993)