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Hierarchical, physical-aware, built-in self-repair of embedded memories. V.R. Devanathan, Harsharaj Ellur, Mohd. Imran, Shivani Bathla Texas Instruments India Pvt. Ltd. {vrd, harsharaj.ellur, m-beg, shivani}@ti.com. 1. Motivation.

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Hierarchical physical aware built in self repair of embedded memories

Hierarchical, physical-aware, built-in self-repair of embedded memories

V.R. Devanathan, Harsharaj Ellur, Mohd. Imran, Shivani Bathla

Texas Instruments India Pvt. Ltd.

{vrd, harsharaj.ellur, m-beg, shivani}@ti.com

1


Motivation
Motivation embedded memories

  • Need area efficient memory test/repair flow over native EDA solution, with support for incremental repair

    • Total test and repair area overhead as high as 1M gate!


Optimizing bist datapath 1
Optimizing BIST datapath embedded memories[1]

Grp4

Grp4

Grp3

Grp3

Grp1

Grp1

Grp5

Grp2

Grp2

Grp5

LEGEND

: Level 0 Group

: Level 1 Group

: Level 2 Group

LEGEND

: Level 0 TIA pipelines

: Level 1 TIA pipelines

: Level 2 TIA pipelines

Pipelines assigned on each data-path

branch using TIA heuristics

Physical-aware grouping of clusters

  • Automated, physical-aware grouping to ease congestion

  • Timing & interconnect-aware pipelining to ease timing closure

[1] V. R. Devanathan, et. al., “Novel approaches for effective and optimized memory test flow in nanoscale technologies”, VTS 2012


Optimizing bira datapath
Optimizing BIRA datapath embedded memories

BIRA

BIRA

BIRA

BIRA

Grp4

Grp4

Grp3

Grp3

Grp1

Grp1

Grp2

Grp2

BIRA

BIRA data-path grouping overview

Grp4

Grp4

BIRA architecture

overview

Grp4

Grp3

Grp3

Grp3

Grp5

Grp1

Grp1

Grp5

Grp1

BIRA

BIRA

BIRA

BIRA

BIRA

BIRA

Grp2

Grp2

Grp2

BIRA

BIRA

BIRA

BIRA

BIRA

BIRA

BIRA execution on Grp2

BIRA execution on Grp4

BIRA execution on Grp3

Grp5

Grp5

Grp5

  • Physical-aware sharing of BIRA across multiple memories

    • Group temporally separated memories, with similar repair code

  • Timing and interconnect-aware BIRA data-path pipelining


Proposed self repair execution flow
Proposed self-repair execution flow embedded memories

M1

M2

M6

M3

M4

M5

FDI

FDI

FDI

FDO

FDO

FDO

FDI

FDO

FDI

FDO

FDI

FDO

BISoR + BIRA

MemGrp1

EFUSE

MemGrp2

FuseROM

PBIST

Test group 1

Soft-repair group 1

Soft-repair group 2

Hard-repair on SoC

Test group 2


Optimizing fuse rom storage
Optimizing Fuse ROM storage embedded memories

INCREMENTAL REPAIR ON MEM1 & MEM3

  • Dynamic re-configuration of memory fuse chain

    • Store only repaired memory data in FuseROM

  • Support for incremental repair with intelligent bypass wrappers

REPAIRING MEM0, MEM2 & MEM5


Robust repair verification flow
Robust repair verification flow embedded memories

  • BIRA & BISoR shared across different memories, with different configurations.

    • Need fool-proof verification on each memory.

FDI

Soft repair

Mem0

FDI

Repair code

BIRA

Mem0

FDI

Mem0

Q

Run BIST with self-repair

Q

Mem_Q

Q

FDO

FDO

Soft unload

FDO

Run BIST with self-repair

Run BIST post-self-repair

PBIST

TCL based fault injection

TCL based fuse register comparator

BISoR

Verification

Complete

PASS

Per-instance unique fail injection

Expected fuse register value

FAIL

Check BISoR

integration /

flow parameters


Results bist and repair data path area
Results: BIST and Repair data-path area embedded memories

PD flylines for level-0 + level-1

datapath routes for a SoC core,without physical-aware flow

PD flylines for level-0 + level-1

datapath routes for a SoC core,with the proposed flow

  • Reduced congestion with proposed BIST/BIRA data-path grouping

  • Significant (~6X) area reduction over native EDA solution


Results fuserom area
Results: FuseROM area embedded memories

  • Significant area reduction without (and with) incremental repair

    • Compaction-based native EDA solution: 2.3X (and ~44%)

    • Proposed dynamic re-configuration: 6.6X (and 4.5X)

  • Compaction (native EDA solution) may be used over the proposed technique for further area reduction


Conclusion
Conclusion embedded memories

  • A novel self-repair flow is presented, that provides

    • ~6X reduction in data-path area, over native EDA flow

    • ~2.5X reduction in FuseROM area, over native EDA flow

    • Automated, physical-design friendly generation of structured BISR data-path

    • Incremental repair support

  • Proposed flow is vendor-agnostic and pluggable into vendor EDA BISR solution


Thank you

Thank You! embedded memories


Built in soft repair bisor controller
Built-In Soft-Repair (BISoR) controller embedded memories

FDI

FDO

FDI

FDI

Mem0

FDI

FDI

Mem0

Repair code

Repair code

Mem0

Q

Mem_Q

Q

Q

Fail encode

BIRA

Mem_ID

fclk

Mem_ID

FCLK

FCLK

FCLK

Mem_fclk[N-1:0]

BISoR

Mem_ID

CG

CG

CG

fuse clock leaker

Fuse_length per mem_ID

Trigger

. . .

0

CG

Bira_fclk

Fuse_clk

  • Soft-repair triggered by PBIST after test of each group.

    • Each BIRA/BISoR is shared across ‘N’ memory groups.


Built in hard repair controller
Built-in Hard-repair controller embedded memories

Memory Fuse Register Chain

fdi

fdo

M0

M1

M2

MM-2

MM-1

W

Fuse auto-load

Fuse auto-unload

EFUSE

Fuse ROM

R

Control / reserved bits

C

W

  • EFUSE controller enhanced for hard-repair

    • Shift out soft-repaired memory fuse chain, slice data wrt FuseROM data-width (W), and automatically blow/write data into FuseROM


Support for incremental repair bisor
Support for incremental repair: BISoR embedded memories

  • Minor enhancements to BIRA and BISoR

    • BIRA: Merging of old repair and new repair code

    • BISoR: Increased clock-leaker pulses and additional trigger

BIRA

Merge

FDI

FDO

Repair code

Mem0

FDI

FDI

Merged repair code

Init repair code

Mem0

FDI

FDI

Mem0

Q

Q

Fail encode

Q

Mem_Q

Mem_ID

fclk

Merge_Trigger

Mem_ID

FCLK

FCLK

FCLK

BISoR

Mem_fclk[N-1:0]

Mem_ID

CG

CG

CG

fuse clock leaker

(2*Fuse_length+1) per mem_ID

Trigger

. . .

0

CG

Bira_fclk

Fuse_clk

Delay (Fuse_length per mem_ID cycles)


Support for incremental repair fuserom
Support for incremental repair: FuseROM embedded memories

  • Bypass wrapper supporting incremental repair


Results bist and repair data path area1
Results: BIST and Repair data-path area embedded memories

  • Negligible (~1%) impact to test time with proposed self-repair flow


Results fuserom area1
Results: FuseROM area embedded memories

  • Significant area reduction without (and with) incremental repair

    • Compaction-based native EDA solution: 2.3X (and ~44%)

    • Proposed dynamic re-configuration: 6.6X (and 4.5X)

  • Compaction (native EDA solution) may be used over the proposed technique for further area reduction