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Simultaneous Time Slack Budgeting and Retiming for DualVdd FPGA Power Reduction. Yu Hu 1 , Yan Lin 1 , Lei He 1 and Tim Tuan 2 1 EE Department, UCLA 2 Xilinx Research Lab Presented by Yu Hu Partially supported by NSF. Address comments to lhe@ee.ucla.edu. Outline.
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Yu Hu1, Yan Lin1, Lei He1 and Tim Tuan2
1EE Department, UCLA
2Xilinx Research Lab
Presented by Yu Hu
Partially supported by NSF.
Address comments to lhe@ee.ucla.edu
[for mixed length wire segments]
[Li, FPGA’04] [Li, DAC’04]
[Li, ICCAD’04] [Gayasen, FPL’04] [Anderson, ICCAD’04] [Lin, DAC’05]
2 units slack needed for a VddL switch insertion
Interconnect Delay
Timing Slack
Combinational Assign
Sequential
Assignment
All VddH Switches !
Movable with Retiming!
VddL Switch Inserted !
/
Placement
/
routing
CLB level
V
dd
assignment
Min

clock retiming
Interconnect
Vdd
assignment
Simultaneous retiming and
interconnect Vdd assignment
Global refinement
Major ContributionsPoweraware postlayout
resynthesis processes:
Sequential vs. Simultaneous
Vdd level assignment for mixed wire segments FPGAs.
53% interconnect power reduction is achieved compared to single Vdd designs.
Simultaneous retiming and interconnect Vdd assignment with flipflop binding constraints. Up to 20% further interconnect power reduction is achieved compared to sequential flow.
[ DualVdd Level Assignment Problem ]
Given: placement and routing results of a FPGA design
Find: A Vddlevel assignment to each interconnect switch
Objective: Minimize interconnect (dynamic and leakage) power
Constraints:
[ Simultaneous Retiming and DualVdd Level Assignment Problem ]
Same to DualVdd level assignment problem in addition to:
Power reduction estimation
Vdd assignment base on estimation
Timing Slack assigned at sinks
b4
b4
b3
b3
b1
b1
b2
b2
S1=1
S1=1
S2=3
S2=3
Review of Vdd Level Assignment Algorithm[Lin, DAC'05]Interconnect power reduction estimation
Problem remained: How to calculate VddL possibility for mixed wire segment?
The netlevel bottomup Vdd assignment guarantees the legalization of final solutions.
[Lin, DAC’05]
Leverage all extra slack with VddL switches
[Lin, DAC’05]
b1, 8x
b3, 16x
S1=6
b2, 8x
S2=10
VddL Possibility Calculationf(2,2) = 1
f(2,3) = 1
f(2,4) = 1/2
L2 = 3
D2 = 12
s2 = 3*(10/12)=5/2
1.7 slack left 1.8 needed!
Only 1.0 VddL switch assignment
b1, 16x, need 1.8 slack
fn(i,1) = 0.9
fn(i,2) = 0.5
lower bound of VddL switches = 0.9 + .5 = 1.4
b2, 8x, need 1.0 slack
Consume 1.0
S = 2.7
S = 2.7
Problem here: Lower bound > actual number!
Sum up all VddL possibility
Dynamic power reduction upper bound
Leakage power reduction upper bound
LP formulation for dualVdd Level AssignmentArrival time for primoutput
Arrival time for priminput
Arrival time constraints
Slack upper bound
Slack constraints
Slack nonnegative
[for mixed length wire segments]
Retiming
The real value a(v) assigned in node v is its arrival time after retiming
linearize
R(v) = r(v) + a(v) /c,
No way to assign this FF in any SLICE physically!
The only timing edge that can insert FFs
FF# can be further reduced!
FF hold time
FF setup time + LUT delay
LUT delay
FF# in edge (e)
[for mixed length wire segments]
[Those circuits with VddL < 85% are selected]
/
Placement
/
routing
CLB level
V
dd
assignment
Min

clock retiming
Interconnect
Vdd
assignment
Simultaneous retiming and
interconnect Vdd assignment
Global refinement
Runtime Efficient CAD FlowSOLUTION
Do Simultaneous Procedureonly when necessary
[for mixed length wire segments]
Q/A
source
b4
b3
b1
b3
b1
b2
b2
s1=2
s1=1
s2=4
s2=1
Timing Slack vs. VddL Switch Number[Dij is the delay increase of the path from source to jth sink by setting VddL to all the switches in this path]
Useful Slack = 3
1 unit slack is needed for VddL
Retiming
r(G) = 1
r(D) = 1
r(F) = 1