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Computer Architecture Notes Jan 26, 2004. Dusan Kuzmanovic Jimmy Ortegon. Machine Instruction Encoding. op. LOAD <ADDR>. <ADDR>. A. a. Three Address Format. 15. 0. op. ADD <30>, <100>, <200>. 30. 100. 200. MEMORY. ALU. CPU. Two Address Format. op. LOAD R1, < > ADD < >, < >

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Computer Architecture Notes Jan 26, 2004


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    1. Computer ArchitectureNotes Jan 26, 2004 Dusan Kuzmanovic Jimmy Ortegon

    2. Machine Instruction Encoding op LOAD <ADDR> <ADDR> A a

    3. Three Address Format 15 0 op ADD <30>, <100>, <200> 30 100 200 MEMORY ALU CPU

    4. Two Address Format op LOAD R1, < > ADD < >, < > ADD R1, R2 ADD <30>, <100> 30 100 MEMORY ALU CPU

    5. One Address Format op ADD <30> 30 MEMORY ALU CPU A

    6. Register to Register Format 2 Register ADD <R1>, <R2> op R1 R2 Second Operand First Operand 3 Register ADD <R1>, <R2>, <R3> op R1 R2 R3 Result Second Operand First Operand

    7. ALU 1 SP ADD IR ALU Zero Address Architecture – or Stack Architecture SP= Stack Memory An stack memory MEMORY S T A C K +

    8. Zero Address Architecture – or Stack Architecture STACK PUSH A ADD POP C REGISTER MEMORY LOAD R1,A ADD R2,R1,B STORE R3, C ACUMMULATOR LOAD A ADD B STORE C LOAD R1,A LOAD R2,B ADD R3,R2,R1 STORE R3 LOAD/ STORE

    9. Sun –Sparc Load/ Store Architecture • INTEL PENTIUM 2 ADDRESS FORMAT WITH OPERAND IN A REGISTER AND THE OTHER IN A REGISTER ON MEMORY

    10. PC MAR IM DM M ADDR OP MDR 1 A ALU DECODER Harvard Architecture Mark-I First Machine DM = Data Memory IM = Instruction Memory

    11. ALU ADDR OP ALU Parallel Instruction Execution PC MAR 2 MAR 1 1 DM IM MULTIPLEXER MDR 1 MDR 2 A DECODER … OV > < = CONDITION CODES

    12. Fetch • MAR1  PC • MDR 1  IM[MAR1] || PC  PC + 1 • IR  MDR 1 • DECODER  IR.OP • NOTE: • JMP depending on < > • PC  IR.ADDR

    13. Load • MAR 2  IR.ADDR • MDR 2  DM[MAR 2] • A  MDR 2

    14. Add • MAR2  IR.ADDR || MAR 1  PC • MDR2  DM[MAR 2] || MDRIM[MAR 1] • A  A + MDR 2 || IR  MDR 1