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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Consumption in a Memory. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsPower Consumption in a Memory Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5970-001/6970-001 Lecture 18

  2. Intuitive Architecture M bits S0 Word 0 Word 1 Storage cell Word 2 N words Word N-2 Word N-1 SN-1 Input-Output (M bits) ELEC 5970-001/6970-001 Lecture 18

  3. Memory Organization Bit line 2L-K Storage cell AK AK-1 AL-1 Word line M.2K Sense amplifiers/drivers A0 AK-1 Column decoder Input-Output (M bits) ELEC 5970-001/6970-001 Lecture 18

  4. Cell Array Power Management • Smaller transistors • Low supply voltage • Lower voltage swing (0.1V – 0.3V for SRAM) • Sense amplifier restores the full voltage swing for outside use. ELEC 5970-001/6970-001 Lecture 18

  5. Sense Amplifier VDD Full voltage swing output bit bit SE Sense ampl. enable: Low when bit lines are precharged and equalized ELEC 5970-001/6970-001 Lecture 18

  6. SRAM Cell VDD Precharge circuit PC EQ WL BL BL Output bit Sense amplifier bit ELEC 5970-001/6970-001 Lecture 18

  7. Hierarchical Organization Block 0 Block 1 Block P-1 Row addr. Column addr. Block addr. Global data bus Control circuitry Global amplifier/driver Block selector I/O ELEC 5970-001/6970-001 Lecture 18

  8. Power Saving • Block-oriented memory • Lengths of local word and bit lines are kept small. • Block address is used to activate the addressed block. • Unaddressed blocks are put in power-saving mode; sense amplifier and row/column decoders are disabled. Power is maintained for data retention. ELEC 5970-001/6970-001 Lecture 18

  9. Static Power 1.3μ 1.1μ 900n 700n 500n 300n 100n 8-kbit SRAM 0.13μ CMOS Leakage current (Amperes) 7x increase 0.18μ CMOS 0.0 0.6 1.2 1.8 Supply voltage ELEC 5970-001/6970-001 Lecture 18

  10. Adding Resistance in Leakage Path VDD Low-threshold transistor sleep VDD.int SRAM cell array SRAM cell array SRAM cell array VSS.int sleep GND ELEC 5970-001/6970-001 Lecture 18

  11. Lowering Supply Voltage VDD VDDL= 100mV for 0.13μ CMOS Sleep = 1, data retention mode sleep SRAM cell array SRAM cell array SRAM cell array GND ELEC 5970-001/6970-001 Lecture 18

  12. References • K. Itoh, VLSI Memory Chip Design, Springer-Verlag, 2001. • J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, Inc., 2003. ELEC 5970-001/6970-001 Lecture 18

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