1 / 108

Synthesis of asynchronous controllers from Signal Transition Graphs:

This paper discusses the synthesis of asynchronous controllers from Signal Transition Graphs (STGs), including topics such as specification, synthesis using the Petrify tool, and advanced concepts. The paper includes examples and diagrams to explain the concepts.

litten
Download Presentation

Synthesis of asynchronous controllers from Signal Transition Graphs:

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Synthesis ofasynchronous controllersfrom Signal Transition Graphs: Jordi CortadellaUniversitat Politècnica de Catalunya Joint work with: Michael Kishinevsky, Intel Corporation Alex Kondratyev, Xilinx Luciano Lavagno, Politecnico di Torino Alex Yakovlev, University of Newcastle Synthesis of async controllers from STGs

  2. Outline • Asynchronous controllers • Specification with Signal Transition Graphs • Synthesis from Signal Transition Graphs • Petrify • Advanced topics Synthesis of async controllers from STGs

  3. Synchronous circuit R CL R CL R CL R CLK Implicit synchronization Synthesis of async controllers from STGs

  4. Asynchronous circuit C C C delay delay delay Aout Ain C L logic L logic L logic L Rin Rout Synthesis of async controllers from STGs

  5. Asynchronous latches: C element A C C B A B C+ 0 0 0 0 1 C 1 0 C 1 1 1 Vdd A B C B A C B A C A B Gnd Synthesis of async controllers from STGs

  6. Data-path / Control L logic L logic L logic L Rin Rout CONTROL Ain Aout Synthesis of async controllers from STGs

  7. Asynchronous modules • Signaling protocol:reqin+ start+ [computation] done+ reqout+ ackout+ ackin+reqin- start- [reset] done- reqout- ackout- ackin-(more concurrency is also possible, e.g. by overlapping the return-to-zero phase of step i-1 with the evaluation phase of step i) DATA PATH Data IN Data OUT start done req in req out CONTROL ack in ack out Synthesis of async controllers from STGs

  8. Memory read cycle Transition signaling, 4-phase Valid address Address A A Valid data Data D D Synthesis of async controllers from STGs

  9. Control specification A+ A B+ B A- A input B output B- Signal Transition Graph (STG) Synthesis of async controllers from STGs

  10. Control specification A+ B+ B A A- B- Assumption: the environment meets the specification Synthesis of async controllers from STGs

  11. Control specification A+ B- B A A- B+ Synthesis of async controllers from STGs

  12. Control specification C A+ B+ A C+ C B A- B- C- Synthesis of async controllers from STGs

  13. Control specification C A+ B+ A C+ C A- B B- C- Synthesis of async controllers from STGs

  14. Control specification Ro+ Ri+ Ri Ro FIFO cntrl Ao+ Ai+ Ao Ai Ro- Ri- Ai- Ao- STG (Petri Net) Synthesis of async controllers from STGs

  15. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  16. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  17. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  18. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  19. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  20. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  21. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  22. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  23. Control specification Ri Ro FIFO cntrl Ao Ai Ro+ Ri+ Ao+ Ai+ Ro- Ri- Ai- Ao- Synthesis of async controllers from STGs

  24. Control specification Ro+ Ri+ Ri Ro FIFO cntrl Ao+ Ai+ Ao Ai Ro- Ri- C C Ai- Ao- Ri Ro Ao Ai Synthesis of async controllers from STGs

  25. A simple filter: specification IN Ain Rin y := 0; loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x; end loop filter Aout Rout OUT Synthesis of async controllers from STGs

  26. A simple filter: block diagram + OUT x y IN Ry Ay Rx Ax Ra Aa Rin Rout control Ain Aout • x and y are level-sensitive latches (transparent when R=1) • + is a bundled-data adder (matched delay between Ra and Aa) • Rin indicates the validity of IN • After Ain+ the environment is allowed to change IN • (Rout,Aout) control a level-sensitive latch at the output Synthesis of async controllers from STGs

  27. A simple filter: control spec. + OUT x y IN Ry Ay Rx Ax Ra Aa Rin Rout control Ain Aout Rout+ Ra+ Ry+ Rx+ Rin+ Aout+ Aa+ Ay+ Ax+ Ain+ Rout- Ra- Ry- Rx- Rin- Aout- Aa- Ay- Ax- Ain- Synthesis of async controllers from STGs

  28. A simple filter: control impl. Rx Ax Aa Ry Ra Ay Aout C Ain Rout Rin Rout+ Ra+ Ry+ Rx+ Rin+ Aout+ Aa+ Ay+ Ax+ Ain+ Rout- Ra- Ry- Rx- Rin- Aout- Aa- Ay- Ax- Ain- Synthesis of async controllers from STGs

  29. Control: observable behavior Rx Ax Aa Ry Ra Ay Aout C Ain Rout Rin Ra- Aa- Ain+ Rin- z Ain- Rin+ Rx+ Ry- z- Ax- Rx- Ay+ Ay- Ax+ Ra+ Aa+ Rout+ Aout+ z+ Rout- Aout- Ry+ Synthesis of async controllers from STGs

  30. x x y y z z Environment Circuit z+ x- x+ y+ z- y- Signal Transition Graph (STG) Synthesis of async controllers from STGs

  31. x y z z+ x- x+ y+ z- y- Synthesis of async controllers from STGs

  32. Taking delays into account x’ z+ x- x y z’ z x+ y+ z- y- Delay assumptions: • Environment: 3 times units • Gates: 1 time unit events: x+  x’-  y+  z+  z’-  x-  x’+  z-  z’+  y-  time: 3 4 5 6 7 9 10 12 13 14 Synthesis of async controllers from STGs

  33. Taking delays into account z+ x- x+ y+ z- y- 0 1 x 0 y 0 1 z very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  34. Taking delays into account z+ x- 1 0 x 0 x+ y+ z- y 0 1 z y- very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  35. Taking delays into account z+ x- 1 0 x 1 x+ y+ z- y 0 1 z y- very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  36. Taking delays into account z+ x- 1 0 x 1 x+ y+ z- y 1 1 z y- very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  37. Taking delays into account z+ x- 0 1 x 1 x+ y+ z- y 1 1 z y- very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  38. Taking delays into account z+ x- failure!!!!! 0 1 x 0 x+ y+ z- y 1 1 z y- very slow Delay assumptions: unbounded delays Synthesis of async controllers from STGs

  39. Delay models for async. circuits DI • Bounded delays (BD): realistic for gates and wires. • Technology mapping is easy, verification is difficult • Speed independent (SI): Unbounded (pessimistic) delays for gates and “negligible” (optimistic) delays for wires. • Technology mapping is more difficult, verification is easy • Delay insensitive (DI): Unbounded (pessimistic) delays for gates and wires. • DI class (built out of basic gates) is almost empty • Quasi-delay insensitive (QDI): Delay insensitive except for critical wire forks (isochronic forks). • Formally, it is the same as speed independent • In practice, different synthesis strategies are used BD SI  QDI Synthesis of async controllers from STGs

  40. Synthesis ofasynchronous controllersfrom STGs Synthesis of async controllers from STGs

  41. x y z Environment Circuit z+ x- x+ y+ z- y- Signal Transition Graph (STG) Synthesis of async controllers from STGs

  42. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist Synthesis of async controllers from STGs

  43. x y z z+ x- x+ y+ z- y- Synthesis of async controllers from STGs

  44. State Graph Generation xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 z+ x- x+ y+ z- y- Synthesis of async controllers from STGs

  45. Next-state functions xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Synthesis of async controllers from STGs

  46. Next-state functions x Env y z In this particular implementation, the circuit generates x and zand the environment generates y. Synthesis of async controllers from STGs

  47. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist Synthesis of async controllers from STGs

  48. VME bus Bus Data Transceiver Device D DSr LDS VME Bus Controller DSw LDTACK DTACK DSr LDS LDTACK D DTACK Read Cycle Synthesis of async controllers from STGs

  49. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK Synthesis of async controllers from STGs

  50. Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Synthesis of async controllers from STGs

More Related