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Energy Efficient CMOS Optical I

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Energy Efficient CMOS Optical I

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    1. Energy Efficient CMOS Optical I/O Samuel Palermo

    2. Outline Introduction 90nm CMOS 16Gb/s optical I/O transceiver Integrated CMOS photonics Conclusion 2

    3. 3 Increasing I/O Bandwidth Demand Single ? Multi ? Many-Core ?Processors Tera-scale many-core processors will aggressively drive aggregate I/O rates

    4. Electrical I/O Channels Frequency dependent loss Caused by dispersion & reflections Exponential with channel distance Equalization circuitry required Power & area overhead Typical commercial electrical I/O xcvr ~20mW/Gb/s at 10Gb/s

    5. Chip-to-Chip Optical Interconnects Optical interconnects remove many channel limitations Reduced complexity and power consumption Potential for high information density with wavelength-division multiplexing (WDM) 5

    6. 90nm CMOS 16Gb/s Optical Transceiver Architecture 6

    7. 7 VCSEL Bandwidth vs Reliability Mean Time to Failure (MTTF) is inversely proportional to current density squared [2] Steep trade-off between bandwidth and reliability

    8. 8 Multiplexing FIR Circuit Implementation

    9. 9 Tap Mux & Output Stage 5:1 multiplexing predriver uses 5 pairs of complementary clock phases spaced by a bit time Tunable delay predriver compensates for static phase offsets and duty cycle error

    10. 10 VCSEL TX Optical Testing

    11. 11 VCSEL 16Gb/s Optical Eye Diagrams

    12. 12 Optical RX Scaling Issues Traditionally, TIA has high RT and low Rin

    13. 13 Integrating Receiver Block Diagram

    14. 14 Demultiplexing Receiver Demultiplexing with multiple clock phases allows higher data rate Data Rate = #Clock Phases x Clock Frequency Gives sense-amp time to resolve data Allows continuous data resolution

    15. 15 Clocked Sense Amplifier Offset cancelled with digitally adjustable PMOS capacitors Step=2.3mV, Range=±70mV Kickback charge can corrupt adjacent bits Need high common-mode input for adequate speed

    16. 16 1V Modified Integrating Receiver Differential Buffer Fixes sense-amp common-mode input for improved speed and offset performance Reduces kickback charge Cost of extra power and noise Input Range = 0.6 – 1.1V

    17. 17 Optical Transceiver Testing

    18. 18 Receiver Sensitivity Test Conditions 8B/10B data patterns (variance of 6 bits) Long runlength data (variance of 10 bits) BER < 10-10

    19. 19 Transceiver Power Consumption Power at 16Gb/s = 129mW (8.1mW/Gb/s) Power scales with data rate Mostly CMOS circuitry Integrating RX sensitivity increases at lower data rates

    20. 20 Optical vs Electrical XCVR Performance Comparisons Compares favorably due to simple equalization circuitry Should scale well Better VCSEL technology Lower capacitance photodetectors Higher data rates ? More equalization for electrical channels

    21. Further Improving Optical I/O Energy Efficiency Leverage ultra-low-power electrical link design techniques Adaptive supply scaling, Source-synchronous clocking Optical component research Longer wavelength VCSEL (850nm -> 1.3mm) Higher speed VCSEL (> 20Gbps) Co-optimization of optical device design and packaging Target 1-2mW/Gbps Monolithically integrated CMOS photonics Waveguide, ring-resonator modulator & detector suitable for CMOS on-die integration Target <1mW/Gbps

    22. Integrated CMOS Photonics 22 Tight integration allows reduced parasitics & improved energy efficiency CPD ˜ 1fF, Cmod ˜ 10fF Challenges Integrating optical devices w/min yield impact Low loss waveguides with high coupling efficiency

    23. Future Photonic CMOS Chip 23 High Bandwidth Interconnect with DWDM Optical Routing Core to Core, Chip to Chip, Core to Memory

    24. Conclusion Optical interconnects provide a path to reducing the I/O bandwidth problem Proposed optical interconnect architecture is suitable for large scale integration in current/future CMOS technologies VCSEL TX equalizer allows low current operation Low voltage integrating receiver Integrated CMOS photonics provides potential for unified intra/inter-chip interconnect with ultimate energy efficiency

    25. 25 Backup Slides

    26. 26 Receiver Sensitivity Analysis

    27. 27 Transceiver Performance Summary

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