1 / 26

Final Design Review of a 1 GHz LNA / Down-Converter

Final Design Review of a 1 GHz LNA / Down-Converter. Charles Baylis University of South Florida April 22, 2005. LNA Design Summary. IBM SiGe Design Kit - 4 layers of metal Load resistance = 50 ohms (Filter)

lindseyl
Download Presentation

Final Design Review of a 1 GHz LNA / Down-Converter

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Final Design Review of a 1 GHz LNA / Down-Converter Charles Baylis University of South Florida April 22, 2005

  2. LNA Design Summary • IBM SiGe Design Kit - 4 layers of metal • Load resistance = 50 ohms (Filter) • Feedback Resistor from collector to base stabilizes circuit, provides better matching • For feedback configuration • IC = 6 mA, RF = 460 ohms (initial – values were changed for final schematic.

  3. LNA Design Summary • Power Consumption: Current through gain transistor + 1 mA reference current through current mirror. • LC Match on Input/Output • “De-Q” Inductors with resistors to improve bandwidth.

  4. LNA Schematic Vcc 7.3 nH 1.4 kΩ 560 Ω 650 Ω 27 pF 4.5 pF Output 6.5 nH 9.3 pF 83 pF Input Ground

  5. LNA Gain

  6. LNA Noise Figure

  7. LNA Input IP3

  8. LNA Input/Output Match

  9. LNA Compliance

  10. LNA Compliance-Temperature

  11. LNA Compliance - Bias

  12. LNA Layout LNA Out LNA In Vcc

  13. Mixer Design Approach • fRF = 1 GHz, fLO = 860 MHz, fIF = 140 MHz • Conversion gain = 9 dB = 2.82 • Output Resistance = 50 ΩRL= 25 Ω • Solve conversion gain equation for gm (gives starting value for current IC1).. • Use LC network for input matching.

  14. Mixer Design Approach • Noise figure improved by shrinking reference transistor for current mirror (and associated current). Also, beta helper transistor size was increased. • As in LNA, “de-Q” inductors with shunt resistors to improve bandwidth.

  15. Mixer Schematic Vcc 7.03 kΩ Out + Out - LO+ LO- 7 kΩ 7.8 nH Input 3.7 pF 83 pF 250 Ω Ground

  16. Mixer Conversion Gain

  17. Mixer Input IP3

  18. Mixer Input/Output Match Input Reflection Coefficient Output Reflection Coefficient

  19. Mixer Noise Figure

  20. Mixer Compliance Specified Gain and Bandwidth

  21. Mixer Compliance - Temperature Specified Gain and Bandwidth

  22. Mixer Compliance - Bias Specified Gain and Bandwidth

  23. Mixer Layout Mixer In Vcc Out + Out - LO +- LO -

  24. LNA DRC and LVS

  25. Mixer DRC and LVS

  26. Conclusion • Only LNA noise figure does not meet specification at nominal temperature and bias. • Design has been run through multiple simulations to test its robustness.

More Related