SRAM Leakage Suppression by Minimizing Standby Supply Voltage

1. SRAM Leakage Suppression by Minimizing Standby Supply Voltage Huifang Qin, Yu (Kevin) Cao, Dejan Markovic, Andrei Vladimirescu, and Jan Rabaey Berkeley Wireless Research Center, University of California, Berkeley As you will find out in the talk, the interest and scope of this work is actually beyond the topic of leakage reduction. This research project is part of the work in BWRC, led by professor Jan Rabaey.As you will find out in the talk, the interest and scope of this work is actually beyond the topic of leakage reduction. This research project is part of the work in BWRC, led by professor Jan Rabaey.

2. - 2 - Outline Motivations SRAM leakage suppression for ultra-low power applications Exploring Ultra-Low Voltage (ULV) SRAM operation capability Modeling The SRAM Data Retention Voltage (DRV) Design and Implementation Dual-rail leakage suppression scheme with ultra-low standby Vdd Measurement Results and Analysis To Minimize the SRAM DRV Conclusion and Future Work At the same time, it is also an exploration on � To tell the whole story of SRAM data retention behavior under ULV, we will start by presenting the analytical modeling of DRV, followed by the design and Implementation of a �, whose purpose is to provide silicon verification for the theoretical analysis. After examining the measurement results we attained from the test chip, we further introduce analysis on the DRV optimization or minimization. In the end, we�ll present a brief overview of the current work of this project and our future direction towards achieving ultra low power and robust design.At the same time, it is also an exploration on � To tell the whole story of SRAM data retention behavior under ULV, we will start by presenting the analytical modeling of DRV, followed by the design and Implementation of a �, whose purpose is to provide silicon verification for the theoretical analysis. After examining the measurement results we attained from the test chip, we further introduce analysis on the DRV optimization or minimization. In the end, we�ll present a brief overview of the current work of this project and our future direction towards achieving ultra low power and robust design.

3. - 3 - Motivation I: Leakage Suppression of Embedded SRAM Nowadays the embedded SRAM circuits in a microprocessor system typically consumes: 90% of the total processor transistor count 60% of the chip area 20% ~ 50% of chip power To explain the motivation behind the efforts of SRAM leakage suppression, let�s first look at several numbers. Given the extremely small feature sizes of today�s state-of-the-art CMOS processes, the transistor count or the chip area may still involve affordable cost; However, the ever-increasing on chip power consumption has become one of our major design bottle neck towards higher performance or lower cost. To be more specific, power efficient design has been critical for applications on both the two ends of performance spectrum. Which is one of the key parameters of the system desirability. Second category of application, more specific, The whole system has to consume less than it can grab from the environment. Quantitative evidencesTo explain the motivation behind the efforts of SRAM leakage suppression, let�s first look at several numbers. Given the extremely small feature sizes of today�s state-of-the-art CMOS processes, the transistor count or the chip area may still involve affordable cost; However, the ever-increasing on chip power consumption has become one of our major design bottle neck towards higher performance or lower cost. To be more specific, power efficient design has been critical for applications on both the two ends of performance spectrum. Which is one of the key parameters of the system desirability. Second category of application, more specific, The whole system has to consume less than it can grab from the environment. Quantitative evidences

4. - 4 - Motivation I: Leakage Suppression of Embedded SRAM To explain the motivation behind the efforts of SRAM leakage suppression, let�s first look at several numbers. Given the extremely small feature sizes of today�s state-of-the-art CMOS processes, the transistor count or the chip area may still involve affordable cost; However, the ever-increasing on chip power consumption has become one of our major design bottle neck towards higher performance or lower cost. To be more specific, power efficient design has been critical for applications on both the two ends of performance spectrum. Which is one of the key parameters of the system desirability. Second category of application, more specific, The whole system has to consume less than it can grab from the environment. Quantitative evidencesTo explain the motivation behind the efforts of SRAM leakage suppression, let�s first look at several numbers. Given the extremely small feature sizes of today�s state-of-the-art CMOS processes, the transistor count or the chip area may still involve affordable cost; However, the ever-increasing on chip power consumption has become one of our major design bottle neck towards higher performance or lower cost. To be more specific, power efficient design has been critical for applications on both the two ends of performance spectrum. Which is one of the key parameters of the system desirability. Second category of application, more specific, The whole system has to consume less than it can grab from the environment. Quantitative evidences

5. - 5 - Motivation II: Exploring Low Voltage SRAM Operation Exactly as what we have observed, supply voltage scaling as been a continuous trend in our design practice. This is because, compared to other architectural or circuit level low power techniques, However, when we are now facing the voltage scaling regime of sub 1V operation, one question everyone has to ask is: when we could possibly scale the Vdd of the logic continuously as before given the support of smart designers in dealing with the degraded speed and exaggerated timing uncertainty, what do we do with memory? There is another behind-the-scene initiative: As supply voltage scales lower and lower and process variations larger and larger, the SNM of SRAM cell is smaller and smaller. The scaling of SRAM reliability with technology evolution is becoming the weakest link in the current and future VSLI design. It has been predicted that at the age of 40~50nm technology node, SRAM designed using current methodology may not be functionable any more� By studying the SRAM voltage limit and its dependence on design factors, this work also provides a view into the robust memory design under normal operation condition.Exactly as what we have observed, supply voltage scaling as been a continuous trend in our design practice. This is because, compared to other architectural or circuit level low power techniques, However, when we are now facing the voltage scaling regime of sub 1V operation, one question everyone has to ask is: when we could possibly scale the Vdd of the logic continuously as before given the support of smart designers in dealing with the degraded speed and exaggerated timing uncertainty, what do we do with memory? There is another behind-the-scene initiative: As supply voltage scales lower and lower and process variations larger and larger, the SNM of SRAM cell is smaller and smaller. The scaling of SRAM reliability with technology evolution is becoming the weakest link in the current and future VSLI design. It has been predicted that at the age of 40~50nm technology node, SRAM designed using current methodology may not be functionable any more� By studying the SRAM voltage limit and its dependence on design factors, this work also provides a view into the robust memory design under normal operation condition.

6. - 6 - The Simple Scheme: SRAM in Ultra-Low Vdd Standby Let�s start with the current designed scheme of Let�s start with the current designed scheme of

7. - 7 - Look Around: Existing Approaches for Low Leakage SRAM Circuit level: Dynamic control of Gate-Source and Substrate-Source Vbias Large design and area overhead Limited saving on leakage power Micro-architectural level: Vdd gating off for idle memory sections Ineffective for caches with large utilization ratio Drowsy cache: put inactive cache lines in a low voltage standby mode Achieves over 70% leakage energy saving in a data cache Question to be answered: how deep a snap can it be? Base our work on a solid ground by looking around to see � Base our work on a solid ground by looking around to see �

8. - 8 - Look Around: What is Unique in This Work A thorough study of ULV SRAM data retention behavior An effective leakage suppression standby scheme for ULP applications The whole SRAM is put in standby mode Maximum leakage saving and minimum design overhead Base our work on a solid ground by looking around to see � Base our work on a solid ground by looking around to see �

9. - 9 - The Data-Retention Voltage (DRV) of SRAM When Vdd scales down to DRV, the Voltage Transfer Curves (VTC) of the internal inverters degrade to such a level that Static Noise Margin (SNM) of the SRAM cell reduces to zero. Unsymmetrical characteristics of the cell transistors � the process variationUnsymmetrical characteristics of the cell transistors � the process variation

10. - 10 - Modeling SRAM DRV Based on the derivation of subthreshold current balance equations and empirical fitting results. 1. Coefficients are function of parameters extracted� 2. Model predicts DRV for the given technology under process and temperature variations, and therefore � Based on the derivation of subthreshold current balance equations and empirical fitting results. 1. Coefficients are function of parameters extracted� 2. Model predicts DRV for the given technology under process and temperature variations, and therefore �

11. - 11 - Design of Dual-Rail SRAM Standby Scheme Standby Vdd noise margin: 100mV Guard band over DRV gives 55mV W.C. SNM Delay overhead A 200�m wide PMOS power switch wakes up the memory in within 10ns Wake up power overhead: Minimum standby time for positive power saving estimated to be around tens of �s. Our goal is to implement the standby scheme, which helps us to achieve silicon verification of the analysis and information for further explorations in this ULV domain. Delay overhead: (small faction of target system cycle time) Wake up power overhead: (much shorter than battery-supported system idle time) Our goal is to implement the standby scheme, which helps us to achieve silicon verification of the analysis and information for further explorations in this ULV domain. Delay overhead: (small faction of target system cycle time) Wake up power overhead: (much shorter than battery-supported system idle time)

12. - 12 - Switch Capacitor (SC) Converter Design Compared to magnetic-based voltage regulators Higher efficiency Smaller current ripple Easier on-chip integration

13. - 13 - 4KB SRAM Leakage Control Scheme Test Chip

14. - 14 - SRAM DRV Measurement

15. - 15 - SRAM Measurement Results Impact of process variation and Drain-Induced-Barrier-Lowering (DIBL) effect causes high leakage in high Vdd conditions. Impact of process variation and Drain-Induced-Barrier-Lowering (DIBL) effect causes high leakage in high Vdd conditions.

16. - 16 - Analysis: What affects SRAM DRV Process variation and temperature fluctuation are the main imperfections in a real environment that cause degradations in circuit performance Process variation: Critical factor for DRV Defines an effective lower bound on SRAM Vdd T: Effect favorable for ultra low power applications Process variation and temperature fluctuation are the main imperfections in a real environment that cause degradations in circuit performance Process variation: Critical factor for DRV Defines an effective lower bound on SRAM Vdd T: Effect favorable for ultra low power applications

17. - 17 - Resize SRAM Cell: for Optimum DRV Poor DRV due to the imbalanced drive under low VddPoor DRV due to the imbalanced drive under low Vdd

18. - 18 - DRV-Aware SRAM Cell Sizing Optimization (NMOS)

19. - 19 - Conclusions and Current Work SRAM DRV modeled and silicon-verified DRV from 80mV to 250mV for 0.13�m technology, 300mV Vth. DRV model facilitates optimization for ULP SRAM design Dual-rail standby scheme saves over 90% Pleakage Effective and low-cost approach for ULP applications DRV can be minimized by: Effective control on process variations (***) Avoid high temperature operation (*) SRAM cell sizing optimization at tradeoffs with speed and area (**) Can we further bring down the SRAM Vdd? A fix at the architecture level may be more effective � use error correction schemes to tolerate ULV errors ULP: battery-supported low duty cycleULP: battery-supported low duty cycle