FPGA Implementation of H.264 Video Encoder. -By Kushal Kunigal under guidance of Dr. K.R.Rao . Spring 2011, Electrical Engineering Department, University of Texas at Arlington. Proposal.
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-By KushalKunigal under guidance of
Electrical Engineering Department,
University of Texas at Arlington
To achieve a real-time H.264 encoding solution, multiple FPGAs and programmable DSPs are often used. The computational complexity alone does not determine if a functional module should be mapped to hardware or remain in software.
Fig 1: H.264 encoder block diagram .
Computational Complexity:Programmable DSPs are bounded in computational complexity, as measured by the clock rate of the processor. Signal processing algorithms implemented in the FPGA fabric are typically computationally-intensive. By mapping these modules onto the FPGA fabric, the host processor or the programmable DSP has the extra cycles for other algorithms. Furthermore, FPGAs can have multiple clock domains in the fabric, so selective hardware blocks can have separate clock speeds based on their computational requirements .
Fig 2: Modules in H.264 video encoder .
Going forward, the motion estimation algorithm will be analyzed from the hardware perspective along with the other modules of the encoder.
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