Power-Aware Architecture

1. Power-Aware Architecture 林光輝 D87921034 鄭伯壎 D90943006 陳盈貝 D90943004 資料來源: ISSCC 2003 Microprocessor Workshop 2003年6月3日

2. Battery technology Linear improvements, nowhere near the exponential power increases we’ve seen Cooling techniques Air-cooled is reaching limits Fans often undesirable (noise, weight, expense) $1 per chip per Watt when operating in the >40W realm Water-cooled ?!? Environment US EPA: significant % of current electricity usage in US is directly due to desktop computers Increasing fast. And doesn’t count embedded systems, Printers, UPS backup? Past: Power important for laptops, cell phones Present: Power a Critical, Universal design constraint even for very high-end chips Circuits and process scaling can no longer solve all power problems. SYSTEMS must also be power-aware Architecture, OS, compilers Why worry about power dissipation

3. Notebook Power Usage Stats 1995 5V Notebook PC From Roy, 1997

4. Processor Power Pie-Chart • High performance processors (prior/current generation) typically burn most of their power in the clocked latches and arrays (registers, caches). (taken from: Bose, Martonosi, Brooks: Sigmetrics-2001 Tutorial) Example data Pre-silicon ckt-sim based; assumes: no clock-gating

5. Power-Performance efficiency • Performance metrics: • delay (execution time) per instruction; MIPS • CPI (cycles per instr): abstracts out the MHz • SPEC (int or fp); TPM: factors in benchmark, MHz • power and energy metrics: • watts (W) and joules (J=W*sec) • joint metric possibilities (perf and power) • Watts (W): for ultra LP processors; also, thermal issues • MIPS/W or SPEC/W ~ energy per instruction • CPI * W: equivalent inverse metric • MIPS2/W or SPEC2/W ~ energy*delay (EDP) • MIPS3/W or SPEC3/W ~ energy*(delay)2 (ED2P)

6. Energy vs. Power • Power metrics (like W): • max power => package design, cost, reliability • average power => avg electric bill, battery life • Energy metrics (like SPEC/W): • compare battery life expectations; given workload • compare energy efficiencies: processors that use constant voltage, frequency or capacitance scaling to reduce power • ED2P metrics (like SPEC3/W or CPI3 * W): • compare pwr-perf efficiencies: processors that use voltage scaling as the primary method of power reduction/control For a systematic and mathematically sound treatment of the metrics issue, i.e. the right choice of k in SPECk/W, see Zyuban et al. ISLPED-02

7. Deducing Optimal Pipe Depths Performance optimal Power-performance optimal MICRO-35 paper (2002; V. Srinivasan et al.)

8. Metrics Comparison (Brooks, Bose et al., IEEE Micro, Nov/Dec 2000) • Note: • at the low end, E metrics like SpecInt/W appear to be fair • at the highest end, ED2P metrics like (SpecInt)3/W seem to do the job • perhaps at the midrange, EDP metrics like (SpecInt)2/W are appropriate?

9. Analysis Abstraction Levels Abstraction Analysis Analysis Analysis Analysis Energy Level Capacity Accuracy Speed Resources Savings Most Worst Fastest Least Most Application Behavioral Architectural (RTL) Logic (Gate) Transistor (Circuit) Least Best Slowest Most Least

10. Power/Performance abstractions at different levels of this hierarchy… • Low-level: • Hspice • PowerMill • Medium-Level: • RTL, Gate-level Models • Architecture-level: • PennState: SimplePower • Intel: Tempest • Princeton: Wattch • IBM: PowerTimer PowerTheater Note: Recent work in statistical performance models is a smart abstraction on top of current detailed simulators (L. Eeckhout, et al., Noonburg and Shen, Carl, Nussbaum, Smith, …)

11. PowerTimer: Power models f(SF) Power linearly dependent on Switching Factor At 0% SF, Power = Clock Power (significant without clock gating)

12. Model Validation • Main challenge: defining a specification reference An Input Testcase GOLDEN REFERENCE MODEL UNDER TEST compare • Secondary problems: • generate apt test cases • test case coverage • choice of o/p signatures outputs Flag Error (if outputs differ)

13. Processors Architecture • Thought for best system level power efficiency • Monolithic processor • Processor + application accelerators • Multi-processor systems • The system is still immature, initial steps using monolithic processors • other choices involve considerable s/w effort

14. Monolithic processors • The PC model • Microarchitectural complexity increases over time to provide more and more performance • superscalar, deep pipes, speculative execution • Traditionally bad for power consumption • need very careful trade off between power and performance • Powering down unused functional units harder • Simplest software platform

15. Accelerator based systems • Core processor for OS + application specific accelerators • Many benefits to modularity • Functional partitioning = power partitioning • easy to control system power • Harder to program generically • OS needs to understand underlying hardware structure • Application specific hardware can be made very power efficient CPU SharedMem. MPEG 3DGx

16. Native Java execution • Interest in Java growing to allow downloadable applications • Many implementation methods • coprocessors, standalone accelerators,… • Inside the core is the most power efficient • allows reuse of execution units • calls to JVM simplified • system design simplified

17. ARM ARM Java Java ARM1136J Java implementation Instruction Pipeline Instruction Stream Execute Unit Thumb Fetch Stage Decode Stage Execute Stage

18. Software for power control • Context specific software power control vital • OS needs to understand how to configure system for lowest power for each execution scenario • enable required functional units • set optimum operating voltage, frequency and body bias • disable everything else • Interaction between h/w and s/w needs to increase dramatically to achieve this

19. System Power Modeling Issues • Need to understand system power components better • where does all the power go in server farms? • system-level power-performance metrics? • relate volumetric power density to system reliability? • MP scalabilty problem – power and performance? • what are the right microarch paradigms of future? • how do we model and design (inductive) noise-aware processors and systems ? • reliabilty vs. performance vs. power tradeoffs