Reorganized and Compact DFA for Efficient Regular Expression Matching

1. Reorganized and Compact DFA for Efficient Regular Expression Matching Publisher : International Conference on Communications (ICC), 2011 Author : Kai Wang, Yaxuan Qi, Yibo Xue, Jun Li Presenter : Yu-Hsiang Wang Date : 2011/09/14

2. Outline • Introduction • Motivation • Algorithm : DFA Reorganization • Architecture • Performance evaluations

3. Introduction • Although D2FA-related algorithms show very good performance in terms of DFA compression ratio, they suffer from nondeterministic memory access per input character. • D2FA can have predictable memory access by limiting the maximum default path length , but at the expense of inefficient and unstable compression performance.

4. Motivation • Due to the large redundancy of identical transitions within similar states in DFA, we can employ the bitmap technique to do compression along the statedimension, called state bitmap. Real DFA table recognizing regular expressions : def[^ef]*add, def[^df]*bee and def[^de]*cff over alphabet {a,b,c,d,e,f,g,h}

5. DFA Reorganization

6. DFA Reorganization

7. DFA Reorganization • Some original transitions along the state dimension are exactly the same, so the unique transition table can be compressed by mapping σμand σνto the same character index, called character mapping.

8. Architecture

9. Performance evaluations

10. Performance evaluations • The memory usage of RCDFA in hardware is tested with limiting the bitmap size to 256 bit and the number of bitmaps to 32

11. Performance evaluations

12. Performance evaluations • We can achieve a maximum clock frequency of 156.01MHz and 2.4Gbps throughput of single RCDFA. • With parallelization of multiple RCDFA matching engines in the test FPGA with 5MB block RAMs, we can further achieve at least (2.4)*5 = 12Gbps throughput for the real-life rule sets in test.