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Networks-on-Chip Ben Abdallah Abderazek The University of Aizu, Graduate School of Computer Science and Eng. Adaptive Systems Laboratory, E-mail: benab@u-aizu.ac.jp 03/01/2010

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networks on chip

Networks-on-Chip

Ben Abdallah Abderazek

The University of Aizu,

Graduate School of Computer Science and Eng.

Adaptive Systems Laboratory,

E-mail: benab@u-aizu.ac.jp

Hong Kong University of Science and Technology, March 2010

03/01/2010

slide2

Part IApplication RequirementsNetwork on Chip: A paradigm Shift in VLSICritical problems addressed by NoCTraffic abstractions Data AbstractionNetwork delay modeling

Hong Kong University of Science and Technology, March 2010

application requirements
Application Requirements
  • Signal processing
  • Hard real time
  • Very regular load
  • High quality
  • Typically on DSPs
  • Media processing
  • Hard real time
  • Irregular load
  • High quality
  • SoC/media processors
  • Multimedia
  • Soft real time
  • Irregular load
  • Limited quality
  • PC/desktop

Very challenging!

Hong Kong University of Science and Technology, March 2010

what the internet needs
What the Internet Needs?

ASIC

(large,

expensive to develop,

not flexible)

SoC, MCSoC?

Increasing Huge

Amount of Packets

&

Routing,

Packet Classification,

Encryption, QoS,

New Applications

and Protocols, etc…..

  • High processing power
  • Support wire speed
  • Programmable
  • Scalable
  • Specially for network applications

General Purpose RISC

(not capable enough)

Hong Kong University of Science and Technology, March 2010

example network processor np
Example - Network Processor (NP)
  • 16 pico-procesors and 1 powerPC
  • Each pico-processor
    • Support 2 hardware threads
    • 3 stage pipeline : fetch/decode/execute
  • Dyadic Processing Unit
    • Two pico-processors
    • 2KB Shared memory
    • Tree search engine
  • Focus is layers 2-4
  • PowerPC 405 for control plane operations
    • 16K I and D caches
  • Target is OC-48

IBM PowerNP

Adaptive Systems Laboratory, Univ. of Aizu

example network processor np6
Example - Network Processor (NP)
  • NP can be applied in various network layers and applications
    • Traditional apps – forwarding, classification
    • Advanced apps – transcoding, URL-based switching, security etc.
    • New apps

Adaptive Systems Laboratory, Univ. of Aizu

telecommunication systems and noc paradigm
Telecommunication Systems and NoC Paradigm
  • The trend nowadays is to integrate telecommunication system on complex multicore SoC (MCSoC):
    • Network processors,
    • Multimedia hubs ,and
    • base-band telecom circuits
  • These applications have tight time-to-market and performance constraints

Adaptive Systems Laboratory, Univ. of Aizu

telecommunication systems and noc paradigm8
Telecommunication Systems and NoC Paradigm
  • Telecommunication multicore SoC is composed of 4 kinds of components:
    • Software tasks,
    • Processors executing software,
    • Specific hardware cores , and
    • Global on-chip communication network

Adaptive Systems Laboratory, Univ. of Aizu

telecommunication systems and noc paradigm9
Telecommunication Systems and NoC Paradigm

This is the most challenging part.

  • Telecommunication multicore SoC is composed of 4 kinds of components:
    • Software tasks,
    • Processors executing software,
    • Specific hardware cores , and
    • Global on-chip communication network

Adaptive Systems Laboratory, Univ. of Aizu

technology architecture trends
Technology & Architecture Trends
  • Technology trends:
    • Vast transistor budgets
    • Relatively poor interconnect scaling
    • Need to manage complexity and power
    • Build flexible designs (multi-/general-purpose)
  • Architectural trends:
    • Go parallel !
    • Keep core complexity constant or simplify
      • Result is lots of modules (cores, memories, offchip interfaces, specialized IP cores, etc.)

Hong Kong University of Science and Technology, March 2010

slide11

Wire Delay vs. Logic Delay

2:1 global on-chip communication to operation delay

9:1 in 2010

Ref: W.J. Dally HPCA Panel presentation 2002

Hong Kong University of Science and Technology, March 2010

slide12

Communication Reliability

  • Information transfer is inherently unreliable at the electrical level, due to:
    • Timing errors
    • Cross-talk
    • Electro-magnetic interference (EMI)
    • Soft errors
  • The problem will get increasingly worse as technology scales down

Adaptive Systems Laboratory, UoA

evolution of on chip communication
Evolution of on-chip communication

Hong Kong University of Science and Technology, March 2010

traditional soc nightmare
Traditional SoC nightmare

DMA

CPU

DSP

Control

signals

CPU Bus

A

Bridge

B

Peripheral Bus

IO

IO

IO

C

Variety of dedicated interfaces

Design and verification complexity

Unpredictable performance

Many underutilized wires

Hong Kong University of Science and Technology, March 2010

network on chip a paradigm shift in vlsi
Network on Chip: A paradigm Shift in VLSI

From: Dedicated signal wires

To: Shared network

s

s

s

Module

s

s

s

Module

Module

s

s

s

Point-

To-point

Link

Computing

Module

Network

switch

Adaptive Systems Laboratory, UoA

noc essential
NoC essential

s

s

s

Module

s

s

s

Module

Module

s

s

s

Communication by packets of bits

Routing of packets through several hops, via switches

Efficient sharing of wires

Parallelism

Hong Kong University of Science and Technology, March 2010

characteristics of a paradigm shift
Characteristics of a paradigm shift
  • Solves a critical problem
  • Step-up in abstraction
  • Design is affected:
    • Design becomes more restricted
    • New tools
    • The changes enable higher complexity and capacity
    • Jump in design productivity

Hong Kong University of Science and Technology, March 2010

characteristics of a paradigm shift18
Characteristics of a paradigm shift

We will look at the problem addressed by NoC.

  • Solves a critical problem
  • Step-up in abstraction
  • Design is affected:
    • Design becomes more restricted
    • New tools
    • The changes enable higher complexity and capacity
    • Jump in design productivity

Hong Kong University of Science and Technology, March 2010

origins of the noc concept
Origins of the NoC concept

The idea was talked about in the 90’s, but actual research came in the new illenium.

Some well-known early publications:

Guerrier and Greiner (2000) “A generic architecture for on-chip packet-switched interconnections”

Hemani et al. (2000) “Network on chip: An architecture for billion transistor era”

Dally and Towles (2001) “Route packets, not wires: on-chip interconnection networks”

Wingard (2001) “MicroNetwork-based integration of SoCs”

Rijpkema, Goossens and Wielage (2001) “A router architecture for networks on silicon”

Kumar et al. (2002) “A Network on chip architecture and design methodology”

De Micheli and Benini (2002) “Networks on chip: A new paradigm for systems on chip design”

Hong Kong University of Science and Technology, March 2010

don t we already know how to design interconnection networks
Don't we already know how to design interconnection networks?

Many existing network topologies, router designs and theory has already been developed for high end supercomputers and telecom switches

Yes, and we'll cover some of this material, but the trade-offs on-chip lead to very different designs!!

Hong Kong University of Science and Technology, March 2010

20

critical problems addressed by noc
Critical problems addressed by NoC

1) Global interconnect design problem:

delay, power, noise, scalability, reliability

2) System integration

productivity problem

3) Chip Multi Processors

(key to power-efficient computing

Hong Kong University of Science and Technology, March 2010

1 a noc and global wire delay
1(a): NoC and Global wire delay

Long wire delay is dominated by Resistance

Add repeaters

Repeaters become latches (with clock frequency scaling)

Latches evolve to NoC routers

NoC Router

NoC Router

NoC Router

Hong Kong University of Science and Technology, March 2010

1 b wire design for noc
1(b): Wire design for NoC
  • NoC links:
    • Regular
    • Point-to-point (no fanout tree)
    • Can use transmission-line layout
    • Well-defined current return path
  • Can be optimized for noise / speed / power
    • Low swing, current mode, ….

Hong Kong University of Science and Technology, March 2010

1 c noc scalability
1(c): NoC scalability
  • For Same Performance, compare the wire area and power

Simple Bus

O(n^3 √n)

O(n√n)

NoC:

O(n)

O(n)

Segmented Bus:

O(n^2 √n)

O(n√n)

Point –to-Point

O(n^2 √n)

O(n √n)

Hong Kong University of Science and Technology, March 2010

1 d noc and communication reliability
1(d): NoC and communication reliability
  • Fault tolerance & error correction

Router

n

Input buffer

UMODEM

U

MO

D

E

M

Router

U

MO

D

E

M

Error correction

Synchronization

UMODEM

ISI reduction

m

Parallel to Serial Convertor

UMODEM

U

MO

D

E

M

Router

U

MO

D

E

M

Modulation

Link Interface

UMODEM

Interconnect

Hong Kong University of Science and Technology, March 2010

A. Morgenshtein, E. Bolotin, I. Cidon, A. Kolodny, R. Ginosar, “Micro-modem – reliability solution for NOC communications”, ICECS 2004

1 e noc and gals
1(e): NoC and GALS
  • Modules in NoC System use different clocks
    • May use different voltages
  • NoC can take care of synchronization
  • NoC design may be asynchronous
    • No waste of power when the links and routers are idle

Hong Kong University of Science and Technology, March 2010

2 noc and engineering productivity
2: NoC and engineering productivity
  • NoC eliminates ad-hoc global wire engineering
  • NoC separates computation from communication
    • NoC supports modularity and reuse of cores
  • NoC is a platform for system integration, debugging and testing

Hong Kong University of Science and Technology, March 2010

3 noc and cmp
3: NoC and CMP

Gate

Interconnect

Diff.

Uniprocessor

dynamic power

(Magen et al., SLIP 200

Uniprocessir

Performance

Die Area (or Power)

  • Uniprocessors cannot provide Power-efficient performance growth
    • Interconnect dominates dynamic power
    • Global wire delay doesn’t scale
    • Instruction-level parallelism is limited
  • Power-efficiency requires many parallel local

computations

    • Chip Multi Processors (CMP)
    • Thread-Level Parallelism (TLP)

Hong Kong University of Science and Technology, March 2010

3 noc and cmp29
3: NoC and CMP
  • Uniprocessors cannot provide Power-efficient performance growth
    • Interconnect dominates dynamic power
    • Global wire delay doesn’t scale
    • Instruction-level parallelism is limited
  • Power-efficiency requires many parallel local computations
    • Chip Multi Processors (CMP)
    • Thread-Level Parallelism (TLP)
  • Network is a natural choice for CMP!

Hong Kong University of Science and Technology, March 2010

3 noc and cmp30
3: NoC and CMP

Network is a natural choice for CMP

  • Uniprocessors cannot provide Power-efficient performance growth
    • Interconnect dominates dynamic power
    • Global wire delay doesn’t scale
    • Instruction-level parallelism is limited
  • Power-efficiency requires many parallel local computations
    • Chip Multi Processors (CMP)
    • Thread-Level Parallelism (TLP)
  • Network is a natural choice for CMP!

Hong Kong University of Science and Technology, March 2010

why now is the time for noc
Why Now is the time for NoC?

Difficulty of DSM wire design

Productivity pressure

CMPs

Hong Kong University of Science and Technology, March 2010

traffic abstractions
Traffic abstractions

PE1

PE2

PE3

PE4

PE12

PE10

PE11

PE5

PE9

PE7

PE8

PE6

Traffic model are generally captured from actual traces of functional simulation

A statically distribution is often assumed for message

Hong Kong University of Science and Technology, March 2010

data abstractions
Data abstractions

Hong Kong University of Science and Technology, March 2010

layers of abstraction in network modeling
Layers of abstraction in network modeling
  • Software layers
    • Application, OS
  • Network & transport layers
    • Network topology e.g. crossbar, ring, mesh, torus, fat tree,…
    • SwitchingCircuit / packet switching(SAF, VCT), wormhole
    • AddressingLogical/physical, source/destination, flow, transaction
    • Routing Static/dynamic, distributed/source, deadlock avoidance
    • Quality of Service e.g. guaranteed-throughput, best-effort
    • Congestion control, end-to-end flow control
  • Data link layer
    • Flow control (handshake)
    • Handling of contention
    • Correction of transmission errors
  • Physical layer
    • Wires, drivers, receivers, repeaters, signaling, circuits,..

Hong Kong University of Science and Technology, March 2010

how to select architecture
How to select architecture ?

Reconfiguration

Rate

During run time

At boot time

At design time

CMP/

Multicore

ASSP

FPGA

ASIC

Flexibility

Single application General purpose or Embedded systems

Architecture choices depends on system needs.

Hong Kong University of Science and Technology, March 2010

how to select architecture36
How to select architecture ?

Reconfiguration

Rate

During run time

At boot time

At design time

A large range of solutions!

CMP/

Multicore

ASSP

FPGA

ASIC

Flexibility

Single application General purpose or Embedded systems

Architecture choices depends on system needs.

Hong Kong University of Science and Technology, March 2010

example oasis
Example: OASIS

K. Mori, A. Ben Abdallah, and K. Kuruda, “Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA", The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.

S. Miura, A. Ben Abdallah, and K. Kuroda, "PNoC - Design and Preliminary Evaluation of a Parameterizable NoC for MCSoCGeneration and Design Space Exploration", The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.

  • ASIC assumed
    • Traffic requirement are known a-priori
  • Features
    • Packet switching – wormhole
    • Quality of service e
    • Mesh topology

Hong Kong University of Science and Technology, March 2010

perspective 1 noc vs bus
Perspective 1: NoC vs. Bus

NoC

Bus

  • Bandwidth is limited, shared
  • Speed goes down as N grows
  • No concurrency
  • Pipelining is tough
  • Central arbitration
  • No layers of abstraction
  • (communication and computation are coupled)
  • However:
  • Fairly simple and familiar

Aggregate bandwidth grows

Link speed unaffected by N

Concurrent spatial reuse

Pipelining is built-in

Distributed arbitration

Separate abstraction layers

However:

No performance guarantee

Extra delay in routers

Area and power overhead?

Modules need NI

Unfamiliar methodology

Hong Kong University of Science and Technology, March 2010

perspective 2 noc vs off chip networks
Perspective 2: NoC vs. Off-chip Networks

NoC

Off-Chip Networks

  • Sensitive to cost:
    • area
    • power
  • Wires are relatively cheap
  • Latency is critical
  • Traffic may be known a-priori
  • Design time specialization
  • Custom NoCs are possible

Cost is in the links

Latency is tolerable

Traffic/applications unknown

Changes at runtime

Adherence to networking

standards

Hong Kong University of Science and Technology, March 2010

vlsi cad problems
VLSI CAD problems

Application mapping

Floorplanning / placement

Routing

Buffer sizing

Timing closure

Simulation

Testing

Hong Kong University of Science and Technology, March 2010

vlsi cad problems in noc
VLSI CAD problems in NoC

Application mapping (map tasks to cores)

Floorplanning / placement (within the network)

Routing (of messages)

Buffer sizing (size of FIFO queues in the routers)

Timing closure (Link bandwidth capacity allocation)

Simulation (Network simulation, traffic/delay/power modeling)

Other NoC design problems (topology synthesis, switching, virtual channels, arbitration, flow control,……)

Hong Kong University of Science and Technology, March 2010

typical noc design flow
Typical NoC design flow

Place Modules

Determine routing and adjust link capacities

Hong Kong University of Science and Technology, March 2010

timing closure in noc
Timing closure in NoC

Define inter-module traffic

Place modules

Increase link capacities

QoS satisfied ?

No

  • Too long capacity results in poor QoS
  • Too high capacity wastes area
  • Uniform link capacities are a waste in ASIP system

Yes

Finish

Hong Kong University of Science and Technology, March 2010

network delay modeling
Network delay modeling
  • Analysis of mean packet delay us wormhole network
    • Multiple Virtual-Channels
    • Different link capacities
    • Different communication demands

Hong Kong University of Science and Technology, March 2010

noc design requirements
NoC design requirements
  • High-performance interconnect
    • High-throughput, latency, power, area
  • Complex functionality (performance again)
    • Support for virtual-channels
    • QoS
  • Synchronization
    • Reliability, high-throughput, low-laten
iso osi network protocol stack model
ISO/OSI network protocol stack model

Hong Kong University of Science and Technology, March 2010

slide47

Part IINoC topologies Switching strategiesRouting algorithmsFlow control schemesClocking schemesQoSBasic Building Blocks Status and Open Problems

Hong Kong University of Science and Technology, March 2010

noc topology
NoC Topology

The connection map between PEs

  • Adopted from large-scale networks and parallel computing
  • Topology classifications:
    • Direct topologies
    • Indirect topologies

Adaptive Systems Laboratory, Univ. of Aizu

direct topologies
Direct topologies

PE

PE

1 PE is

connected

to only a single SW

SW

SW

PE

PE

SW

SW

Each switch (SW) connected to a single PE

As the # of nodes in the system increases, the total bandwidth also increases

Hong Kong University of Science and Technology, March 2010

direct topologies mesh
Direct topologiesMesh
  • 2D mesh is most popular
    • All links have the same length
      • Eases physical design
    • Area grows linearly with the the # of nodes

Hong Kong University of Science and Technology, March 2010

4x4 Mesh

direct topologies torus and folded torus
Direct topologiesTorus and Folded Torus
  • Similar to a regular Mesh
  • Excessive delay problem due to long-end-around connection
  • Overcomes the long link limitation of a 2-D torus
  • Links have the same size

Hong Kong University of Science and Technology, March 2010

direct topologies octagon topology
Direct topologiesOctagon topology

PE

PE

PE

SW

PE

PE

PE

PE

PE

Messages being sent between any 2 nodes require at most two hops

More octagons can be tiled together to accommodate larger designs

Hong Kong University of Science and Technology, March 2010

indirect topologies
Indirect topologies

A set of PEs are connected to a switch (router).

SW

SW

SW

SW

SW

SW

SW

PE

PE

PE

PE

PE

PE

PE

PE

Hong Kong University of Science and Technology, March 2010

  • Fat tree topology
    • Nodes are connected only to the leaves of the tree
    • More links near root, where bandwidth requirements are higher
indirect topologies k ary n fly butterfly network
Indirect topologiesk-ary n-fly butterfly network

Example: 2-ary 3-fly butterfly network

  • Blocking multi-stage network – packets may be temporarily blocked or dropped in the network if contention occurs

Hong Kong University of Science and Technology, March 2010

indirect topologies m n r symmetric clos network
Indirect topologies(m, n, r) symmetric Clos network
  • 3-stage network in which each stage is made up of a number of crossbar switches
  • m : number of middle-stage switches
  • n : number of input/output nodes on each input/output switch
  • r : number of I and O switches

Example: (3, 3, 4) Clos network

  • Non-blocking network
  • Expensive (several full crossbars)

Hong Kong University of Science and Technology, March 2010

indirect topologies benes network
Indirect topologiesBenes network
  • Example: (2, 2, 4) re-arrangeable Clos network constructed using two (2, 2, 2) Clos networks with 4 x 4 middle switches.

Rearrangeable network in which paths may have to be rearranged to provide a connection, requiring an appropriate controller

Clos topology composed of 2 x 2 switches

Hong Kong University of Science and Technology, March 2010

irregular topologies customized
Irregular TopologiesCustomized

PE

sw

PE

PE

sw

sw

sw

sw

sw

PE

PE

PE

sw

sw

sw

sw

sw

sw

sw

PE

PE

PE

PE

PE

PE

PE

PE

PE

sw

PE

sw

sw

PE

sw

sw

sw

sw

PE

PE

sw

sw

sw

sw

sw

sw

PE

PE

PE

PE

PE

PE

Example 2: Cluster-based hybrid topology

Example1: Reduced mesh

Hong Kong University of Science and Technology, March 2010

Customized for an application

Usually a mix of shared bus, direct, and indirect network topologies

example 1 partially irregular 2d mesh topology
Example 1: Partially irregular 2D-Mesh topology
  • Contains oversized rectangularly shaped PEs.

Adaptive Systems Laboratory, Univ. of Aizu

example 2 irregular mesh
Example 2: Irregular Mesh
  • This kind of chip does not limit the shape of the PEs or the placement of the routers. It may be considered a "custom" NoC

Adaptive Systems Laboratory, Univ. of Aizu

how to select a topology
How to Select a Topology ?

Application decides the topology type

If PEs = few tens

Star, Mesh topologies are recommended

If PEs = 100 or more

Hierarchical Star, Mesh are recommended

Some topologies are better for certain designs than others

Most of the times, when one topology is better in performance, it is worse in power consumption!!

Adaptive Systems Laboratory, Univ. of Aizu

slide61

Part IINoC topologies NoC Switching strategiesRouting algorithmsFlow control schemesClocking schemesQoSBasic Building Blocks Status and Open Problems

Hong Kong University of Science and Technology, March 2010

noc switching strategies
NoC Switching Strategies

Switching determines how flits and packets flows through routers in the network

  • There are two basic modes:
    • Circuit switching
    • Packet switching

Adaptive Systems Laboratory, Univ. of Aizu

circuit switching
Circuit Switching

Network resources (channels) are reserved before a packet is sent

Entire path must be reserved first

The packets do not contain routing information, but rather data and information about the data.

Circuit-switched networks require no overhead for packetisation, packet header processing or packet buffering

Hong Kong University of Science and Technology, March 2010

circuit switching64
Circuit Switching

Header

ACK

Data

R1

R2

R3

Router

Delay

Routing + switching delay

Setup time

Transfer time

Adaptive Systems Laboratory, Univ. of Aizu

circuit switching65
Circuit Switching
  • Once circuit is setup, router latency and control overheads are very low
  • Very poor use of channel bandwidth if lots of short packets must be sent to many different destinations
    • More commonly seen in embedded SoC applications where traffic patterns may be static and involve streaming large amounts of data between different IP blocks

Hong Kong University of Science and Technology, March 2010

packet switching
Packet Switching

We can aim to make better use of channel resources by buffering packets. We then arbitrate for access to network resources dynamically.

We distinguish between different approaches by the granularity at which we reserve resources (e.g. channels and buffers) and conditions that must be met for a packet to advance to the next node

Hong Kong University of Science and Technology, March 2010

packet switching67
Packet Switching

Advance when entire packet is buffered + L free flit buffers at next node

Store-and-forward (SaF)

Packet-Buffer

Flow Control

Advance when L free flit buffers at the next node

Cut-through

Can advance when at least one flit buffer is available

Flit-Buffer

Flow Control

Wormhole

L : Packet Length

Hong Kong University of Science and Technology, March 2010

packet switching store and forward saf
Packet Switching Store and Forward (SAF)

Forward packet by packet

Buffer

Buffer

Buffer

Switch

Switch

Switch

packet

Store and Forward switching

data flit header flit

  • Packet is sent from one router to the next only if the receiving router has buffer space for entire packet
  • Buffer size in the router is at least equal to the size of a packet

Hong Kong University of Science and Technology, March 2010

packet switching wormhole wh
Packet switching Wormhole (WH)

Forward flit by flit

Buffer

Buffer

Buffer

packet

Switch

Switch

Switch

WH switching technique

data flit header flit

  • Flit is forwarded to a router if space exists for that flit
  • Parts of the packet can be distributed among two or more routers
  • Buffer requirements are reduced to one flit, instead of an entire packet

Hong Kong University of Science and Technology, March 2010

packet switching virtual channel vc
Packet switching Virtual Channel (VC)
  • Improve performance of WH routing, prevent a single packet blocking a free channel
    • e.g. if the green packet is blocked, the red packet may still make progress through the network
    • We can interleave flits from different packets over the same channel

Hong Kong University of Science and Technology, March 2010

slide71

Part IINoC topologies NoC Switching strategiesRouting algorithmsFlow control schemesClocking schemesQoSBasic Building Blocks Status and Open Problems

Hong Kong University of Science and Technology, March 2010