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ECE 366 -- Computer Architecture Lecture Notes # 6. Shantanu Dutt How to Add To & Use the Basic Processor Organization To Execute Different Instructions. Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+X]. Determine Phases (each may take >= 1cc and may be further decomposed):

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ece 366 computer architecture lecture notes 6

ECE 366 -- Computer ArchitectureLecture Notes # 6

Shantanu Dutt

How to Add To & Use the Basic Processor Organization To Execute Different Instructions

instruction lw ri x 16 bit offset r1 mem pc x
Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+X]
  • Determine Phases (each may take >= 1cc and may be further decomposed):
    • 1. Instruction Fetch: Same for all instr. of the same size (32 bits here)
    • 2. Decode & Incr. PC (same as before). Note that X is offset from new PC value
    • 3. Compute the address (PC+x) of the data to be fetched
      • Requirements & Options:

(I) F.U.: (a) Adder: Useadders avail (which?) OR Put in a new adder. (b) Need a sign extender for X (16 to 32 bits)

(II) Registers: A data address reg. to store PC+X

(III) (a) Connections from PC & X to Adder; (b) Connection from MAR to mem. address bus

instruction lw ri x 16 bit offset r1 mem pc x3
Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+X]
  • Phases:
    • 4. Fetch Data
      • Requirements & Options:

(I) F.U.: None

(II) Registers: A data reg. (MDR) to load data on the memory data bus

(III) (a) Connections from mem data bus to MDR

    • 5. ri <== MDR
      • Requirements & Options:

(I) F.U.: None

(II) Registers: None

(III) (a) Connections from MDR to write port of reg. file

instruction processing phase 1 fetch

Data Memory

Memory Interface (Buses + Regs)

Register

File

ALU

O/P Reg.

Instruction Processing: Phase 1 -- Fetch

Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+x]

Instruction Memory

Memory Interface (Addr. + Data Bus)

Source & dest reg addr

PC

IR

1

1

PC

Upd.

Load IR when

Instr. Avail

[IR <= Data Bus]

Connect PC to Addr. Bus &

Read Mem. Onto Data Bus

C.U.

FSM

Status signals

[PC=>Addr Bus; Mem[PC] => Data Bus]

instruction processing phase 2 decode incr pc

Data Memory

Memory Interface (Buses + Regs)

Register

File

ALU

O/P Reg.

Instruction Processing: Phase 2 -- Decode & Incr. PC

Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+x]

Instruction Memory

Memory Interface (Addr. Bus)

PC

IR

2

PC

Upd.

Decode State

2

Start State for lw

Load PC w/ o/p

of Update H/W

[PC <= PC Upd o/p]

C.U.

FSM

adding extra hardware for lw mar mdr

Data Memory

Adding extra hardware for “lw”: MAR & MDR

Instruction Memory

Instruction: lw ri x(16-bit offset) [ri <= MEM[PC+x]

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

IR

PC

Source & dest reg addr

4

Register

File

+

.

MUX

C.U.

FSM

ALU

Status signals

O/P Reg.

adding extra hardware for pc x design 1

Data Memory

Adding extra hardware for PC+X: Design 1

Instruction Memory

Design 1: Put in extra adder---(a) Expensive in logic and interconnects; (b) Time = 1cc (if + takes 1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

MUX

16->32 ext.

32

+

.

C.U.

FSM

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 design 1

Data Memory

Instruction Processing: PC+X :Phase 3--Design 1

Instruction Memory

1cc operation (if + takes 1 cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

Load MAR

MUX

16->32 ext.

32

+

.

C.U.

FSM

ALU

Status signals

O/P Reg.

adding extra hardware for pc x design 2

Data Memory

MUX

MUX

Adding extra hardware for PC+X: Design 2

Instruction Memory

Design 2: Use ALU adder---(a) Better but a little exp. in interconnects & MUXes; (b) Time = 3cc (if + takes 1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

MUX

16->32 ext.

32

.

C.U.

FSM

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 a design 2

Data Memory

Instruction Processing: PC+X :Phase 3(a)--Design 2

Instruction Memory

3cc entire operation: Phase 3(a) Load offset and PC in ALU reg (1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

MUX

16->32 ext.

32

.

Select offset, PC

MUX

MUX

C.U.

FSM

Load ALU regs

Status signals

ALU

O/P Reg.

instruction processing pc x phase 3 b design 2

Data Memory

MUX

MUX

Instruction Processing: PC+X :Phase 3(b)--Design 2

Instruction Memory

3cc entire operation: Phase 3(b) ADD in ALU, Load o/p reg. (1cc if + is 1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

MUX

16->32 ext.

32

.

C.U.

FSM

Select Add

+

.

Status signals

ALU

Load o/p reg.

O/P Reg.

instruction processing pc x phase 3 c design 2

Data Memory

MUX

MUX

Instruction Processing: PC+X :Phase 3(c)--Design 2

Instruction Memory

3cc entire operation: Phase 3(c) MAR <= o/p reg.

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

PC

IR

Source & dest reg addr

4

Register

File

16

+

.

Load MAR

MUX

16->32 ext.

32

.

C.U.

FSM

ALU

Status signals

O/P Reg.

adding extra hardware for pc x design 3

Data Memory

+

.

MUX

Adding extra hardware for PC+X: Design 3

Instruction Memory

Design 3: Use PC adder---(a) Slightly less expensive than opt. 2; (b) Time = 1cc (if + takes 1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

Source & dest reg addr

Register

File

16

MUX

16->32 ext.

32

C.U.

FSM

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 design 3

Data Memory

Instruction Processing: PC+X :Phase 3--Design 3

Instruction Memory

1cc operation (if + takes 1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

Source & dest reg addr

MUX

Register

File

16

Read offset

Load MAR

MUX

16->32 ext.

+

.

32

C.U.

FSM

ALU

Status signals

O/P Reg.

adding extra hardware for pc x design 4

Data Memory

Register

File

+

.

Adding extra hardware for PC+X: Design 4

Instruction Memory

Design 4: Use PC adder & Write Bus interconnection---(a) Least exp. & most general (applicable to other instr); (b) Time is slowest: 5cc for a 1 write port reg. file

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

16

16->32 ext.

32

Source & dest reg addr

C.U.

FSM

Write Bus

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 a design 4

Data Memory

Register

File

+

.

Instruction Processing: PC+X :Phase 3(a)--Design 4

Instruction Memory

5 cc entire operation: Phase 3(a): Load scratchpad reg0 (sr0) from PC -- 1cc

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

16

16->32 ext.

Read PC

[WB <=PC]

Load sr0

[sr0<=WB]

32

C.U.

FSM

Write Bus

Source & dest reg addr

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 b design 4

Data Memory

Register

File

+

.

Instruction Processing: PC+X :Phase 3(b)--Design 4

Instruction Memory

5 cc entire operation: Phase 3(b): Load scratchpad reg1 (sr1) from offset-- 1cc

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

16

Read offset

[WB<=offset]

16->32 ext.

Load sr1

[sr1<=WB]

32

C.U.

FSM

Write Bus

Source & dest reg addr

ALU

Status signals

O/P Reg.

instruction processing pc x phase 3 c design 4

Data Memory

Register

File

+

.

Instruction Processing: PC+X :Phase 3(c)--Design 4

Instruction Memory

5 cc entire operation: Phase 3(c): Read sr0 and sr1 and load ALU I/p regs (1cc)

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

16

16->32 ext.

Read sr0 & sr1

32

C.U.

FSM

Source & dest reg addr

Write Bus

Load ALU regs

Status signals

ALU

O/P Reg.

instruction processing pc x phase 3 d design 4

Data Memory

Register

File

+

.

Instruction Processing: PC+X :Phase 3(d)--Design 4

Instruction Memory

5 cc entire operation: Phase 3(d): ADD and load o/p reg.

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

16

16->32 ext.

32

Source & dest reg addr

C.U.

FSM

Write Bus

Select Add

+

Status signals

ALU

Load o/p reg.

O/P Reg.

instruction processing pc x phase 3 e design 4

Data Memory

Register

File

+

.

Instruction Processing: PC+X :Phase 3(e)--Design 4

Instruction Memory

5 cc entire operation: Phase 3(d): Read o/p reg. to WB, load MAR --1cc

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

Load MAR

[MAR <=WB]

16

16->32 ext.

32

Source & dest reg addr

C.U.

FSM

Write Bus

ALU

Status signals

Read o/p reg.

[WB <= o/p reg.]

O/P Reg.

instruction proc data fetch in lw phase4 design 4

Data Memory

Register

File

+

.

Instruction Proc: Data Fetch in “lw”: Phase4 -- Design 4

Instruction Memory

>= 1cc operation (based on memory speed); will need to “wait” in this state until operation is completed

Memory Interface (Addr + Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

Read mem

MDR

4

PC

IR

Read MAR to Addr. Bus

16

16->32 ext.

Load MDR when

data available

32

Source & dest reg addr

C.U.

FSM

Write Bus

ALU

Status signals

O/P Reg.

instr proc performing ri mdr phase 5 design 4

Data Memory

+

.

Instr Proc: Performing ri <= MDR: Phase 5 -- Design 4

Instruction Memory

1cc operation

Memory Interface (Data Bus)

Memory Interface (Addr. + Data Bus)

MAR

MDR

4

PC

IR

Read MDR onto WB

[WB <= MDR]

16

16->32 ext.

Write to ri using dest.

reg. addr. from IR

32

Register

File

C.U.

FSM

Write Bus

Source & dest reg addr

ALU

Status signals

O/P Reg.

some control unit fsm design tips
Some Control Unit FSM Design Tips
  • The CU FSM is a Moore M/C; it is easier to reason about and design since instruction processing actions (i.e., control signals, which are the o/ps of the CU FSM) are associated w/ states
  • The sequence [reg(s) read --> processing of resulting data --> reg(s) write] needs to be performed in a single state
  • Different sequences of the above type need to be performed in different states if either: (a) there is a data dependency between them or (b) they need to share hardware resources (e.g., the internal write bus, the ALU adder)
  • A particular sequence of the above type can take > 1 cc (e.g., instruction or data fetch from memory) in which case the CU generally needs to loop in a single state until a status signal (which is an i/p to the FSM) is received indicating completion of the operation
some control unit fsm design tips contd
Some Control Unit FSM Design Tips (contd.)
  • If in the sequence [reg(s) read --> processing of resulting data --> reg(s) write] the destination reg(s) can be the same as the source reg(s) (reg(s) read) AND this sequence can take > 1 cc, then a race condition can occur, which can give a final incorrect result
  • A race condition is one in which the o/p feeds back to the i/p before the operation is completed. This results in the i/p to the operation changing midway during the operation, thus resulting potentially in an incorrect o/p.