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Team XOR

Team XOR. deSIGN PROPOSAL FOR DSP. 29 April 2010. Domenic Carr Jae Park Daniel Reyno. Sizing of Circuit ( V m ). Minimize WC Delay Most Important Metric Originally 2:1 Ratio 3 to 1.5 (in µm) Optimize P:N Ratio 2.33 to 1.5 (in µm) Also Reduces Area. AND/OR/NOP/PASS: CMOS or Pass?.

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Team XOR

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  1. Team XOR deSIGN PROPOSAL FOR DSP 29 April 2010 Domenic Carr Jae Park Daniel Reyno

  2. Sizing of Circuit (Vm) • Minimize WC Delay • Most Important Metric • Originally 2:1 Ratio • 3 to 1.5 (in µm) • Optimize P:N Ratio • 2.33 to 1.5 (in µm) • Also Reduces Area

  3. AND/OR/NOP/PASS: CMOS or Pass? • CMOS Logic • No Buffers/Inv Inputs • AND Gate: 14.49µm • OR Gate: 16.15µm • 16AND+16OR=490.24µm • Saves Area • Pass Gate Logic • Buffers (+7.66u) and Inverted Inputs (+3.83u) • AND Gate: 16.82u • OR Gate: 17.65u • 16AND+16OR=551.52µm

  4. Mirror Adder Topology Utilizes Kill/Propagate/Generate property of bitwise addition for quick calculation of carry out bits.

  5. Adder/Subtractor To include subtraction functionality, we simply augmented our base adder with extra hardware (17 2:1 MUXes and 9 inverters) to implement two’s complement subtraction.

  6. Barrel Shifter • WC: Pass thru 1 NMOS • TX Gates Variation: • Larger Tapered Buffers • Buffer Regeneration • A only loads buffer • Total = 308.18u

  7. Other Shifter Implementations • 4:1/2:1 MUX Variation • 4:1 MUX = 49.79 (includes buffering) • Total = 796.64u • TX Gate Variation • 16(2INV + TX) =(306.4u) • With Decoder (65.62u) • Total = 372.02u

  8. Shifter Decoder (w/ and w/o PassA) • B1B0 loads 1 INV, 2 AND = 14.49u • Pass A (separately) • Total = 430.74u • PassA (w/ Shifter) • 8 3-input NANDs, 1 4-input OR, 3 inverters • Total = 465.08u

  9. 3 Generations of MUX Technology

  10. Gen1 MUX Technology Area of 16 Gen1 MUXes: 7,271 µm -3 Inverters -8 4-input AND gates -1 8-input OR gate

  11. Gen2 MUX Technology Implemented Predecoding scheme (left) and simplified 8-input OR gate to series of 2-input NANDS and 2-input NORS (right)

  12. Gen2 MUX Technology Gen2 MUX Technology had total area of 5,577.44 micrometers. The entire ALU would have had an area of 12,204.48 micrometers.

  13. Gen3 MUX Technology 7 2:1 MUXes 6 Buffers

  14. Gen3 MUX Technology Gen3 MUX Technology had total area of 2,022 micrometers. The entire ALU now had an area of 8,649 micrometers.

  15. Multiplier

  16. Multiplier Metric • Delay: 6.75 ns • Area: 8554.16 µm • Energy: 531 pJ/op

  17. Function Enabler • Decoder that used control lines to determine which function should be powered by VDD • Motivations: • 128 possible operations occurring in parallel during any given cycle – Lots of wasted power • Desirable to have only the 16 relevant bits calculated

  18. VDD Analysis • VDD = 2.5V • Delay: 18.95 ns • Area: 8649.28 um • Power: 125 pJ/op • Metric: • 3.88 * 10-28 [s2*m*J/op] • VDD = 4V • Delay: 10.05 ns • Area: 8649.28 um • Power: 389 pJ/op • Metric: • 3.71 * 10-28 [s2*m*J/op]

  19. Metrics (VDD=5V) • Circuit (w/o MULT) • Delay: 8.83 ns • Area: 8649.28 um • Energy: 540 pJ/op • Total Metric: • 3.637 * 10-28 [s2*m*J]

  20. Questions?

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