ELEC 692 Special Topic VLSI Signal Processing Architecture Fall 2004

1. ELEC 692 Special Topic VLSI Signal Processing ArchitectureFall 2004 Chi-ying Tsui Department of Electrical and Electronic Engineering HKUST eetsui@ee.ust.hk Rm: 2522

2. Course Description • ELEC692 is dedicated for advanced Digital VLSI architecture for high performance and low power digital signal processing, particularly for communication and multimedia applications • General design and transformation techniques will be discussed for the optimization of the computation and architecture • pipelining, retiming, folding and unfolding, and systolic array design will be discussed • algorithmic/architectural tradeoff in power and performance will be studied • example applications in video processing and wireless communication architectures will be provided. • Specialized Application specific VLSI Architectures will be discussed if time permits. • Extensive use of CAD tools and HDL modeling - Synopsys and Cadence Tools • Design project

3. Course Objectives • This course reviews the design of VLSI architecture and design methodologies for digital signal processing for multimedia and communication applications. Application-specific processors and architectures to support real time processing of digital signals for different applications will be studied. Upon completion of this course, students will attain the following: • knowledge on designing high performance and low power architectures for different signal processing applications • methodology of designing VLSI implementation for different signal processing applications from the algorithmic level down to circuit level • understanding the algorithmic/architectural tradeoff for designing a signal processing applications • hand-on experience of using state-of-the-art CAD tools on designing such kind of architecture

4. Text and Reference Books • Major Text: • K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley and Sons, 1999. • P. Pirsch, Architecture for Digital Signal Processing, John Wiley and Sons, 1998. • Selected papers from IEEE Transactions and other Journals

5. Course Grading • Homework: 30% • 3 to 4 written assignments • Paper project 25% • Literature review on a special topic. • Presentation and written paper are required. • Individual project • Design project: 45% • Group or individual project: Personal per group ~ 2 • Team work is important • Design an architecture for a signal processing algorithm • Tasks to be finished • Specification: High-level model • Logic Design: Synthesis and simulation • Layout Design of critical block • Verification - simulation for different abstraction level • Final Layout of the chip (Optional) • Performance estimation of the chip (Optional)

6. Lecture Outline • The course is delivered through lectures. The following topics will be covered in the course: • Introduction • Overview on Typical Signal Processing Algorithms • Overview of VLSI Architectures • Basic signal processing kernel algorithm: digital filter, linear transformation • General signal processing architecture design techniques • Pipelining • Parallel Processing • General algorithm transformation techniques: • Retiming • unfolding algorithm • Folding Transformation • Register Minimization

7. Lecture Outline • Systolic array structure and design methodology • Mapping of algorithm to array structures • Low Power design of digital signal processing systems • Programmable digital signal processor architectures: • Architecture and programming issues • DSP Processors for Mobile and Wireless Communications • Re-configurable computing using Field Programmable Gate Array (FPGA) • Signal processing arithmetic applications: • Distributed arithmetic, CORDIC • FFT/IFFT, DCT/IDCT • VLSI signal processing architecture for multimedia applications • JPEG/MPEG • Motion estimation architecture • VLSI signal processing architecture for communication applications • Network processor architecture • Digital modulation systems such as OFDM • VLSI architecture for channel error correction coding such as Viterbi decoder, Turbo code decoder

8. Teaching Team • Instructor: • Dr. Chi-ying Tsui(eetsui@ee) • Tel: 2358-7071 • Office: Rm. 2522 • Office hour: Tuesday. 4-6p.m. • Technician (by email or appointment) : • Mr. Jeff Lam(jeff@ee) • Tel: 2358-8844 • Office: Rm: 3114b http://www.ee.ust.hk/~elec692

9. Assumed Background knowledge • Basic CMOS circuit theory and design technique • resistance, capacitance, inductance • MOS gate characteristics • Different CMOS logic design technique • Basic performance evaluation • Use of modern EDA tools • simulation, validation (HSPICE) • schematic capture tools (Cadence) • Logic design • logical minimization, FSMs, component design