ภาษาเครื่อง

1. บทที่ 5 ภาษาเครื่อง Micro Program ไมโครโปรแกรม

2. Model of Control Unit How the Control Unit Generate the control signal?

3. Model of Control Unit • Get instruction from Instruction Register • Working steps with the timing generator and conditions from flag, the signal from IR passed through the Decoder circuit into the CU to generate the control signal out.

4. Block Diagram of the Control Unit

5. Control Unit with Decoded Inputs

6. Microprograms? • 1950 Maurice V. Wikes (Cambridge Univer.) • IBM System/360 to achieve instruction-set compatibility across many models. • Microprogramming allows a CPU’s program control unit : PCU to be designed sequences known as Microprograms are placed in a special control memory in the CPU.

7. Wilkes's Microprogrammed Control Unit

8. Microprograms? - so that instruction from the CPU’s main instruction set is executed by invoking and executing the corresponding microprogram. * * * * * * * CPU with no floating-point arithmetic circuits can execute by means of fixed-point arithmetic circuits.

9. Digital Systems : CPU • Data Path Unit network offunctional and storage units capable of performing certain operation on data words. • Control Unit issue control signal to the data path for selecting the function to be performed at specific times and route through the appropriate parts of the datapath unit.

10. Data Paths and Control Signals

11. Digital Systems : CPU • Hardwired fixed logic circuits to generate the control signals. • Microprogrammed stores the control signals in sequence of micro-instructions (microprograms) in a control memory. * provide a systematic & flexible method *

12. Microprogrammed Control Use microprograms to select, interpret, and execute instruction set. Fig. 15.4 CU contain logic to generate micro-instruction addresses and to fetch and decode from control memory.

13. Control Unit Microarchitecture

14. Basic Concepts Instruction is implemented by a sequence of one or more sets of concurrent micro-operations. Each micro-operation is associated with a group of control lines that must be activated in a prescribed sequence to trigger the micro-operations.

15. Basic Concepts . . . Program Execution Instruction Cycle Instruction Cycle . . . Fetch Execute Interrupt . . . mOP mOP mOP

16. Basic Concepts Microprogramming is a method of control-unit design in which the control signal selection and sequencing information is stored in a ROM or RAM called . . . . . ControlMemory : CM

17. Functioning of Microprogrammed Control Unit

18. Basic Concepts The control signals could be activated at any time that are specified by a micro-instruction, which is fetched from CM in much the same way an instruction is fetched from main memory.

19. Basic Concepts Instruction Cycle • Fetch • Indirect • Execute • Interrupt

20. Flowchart for Instruction Cycle

22. Basic Concepts Fetch Cycle3 steps and 4 micro-operations t1 : MAR <--- (PC) t2 : MBR <--- Memory PC <--- (PC) + I t3 : IR <--- (MBR) I: Instruction Length

23. Sequence of Events, Fetch Cycle

24. Basic Concepts Indirect Cycle3 micro-operations t1 : MAR <--- (IR (address)) t2 : MBR <--- Memory t3 : IR(Address) <--- (MBR(address))

25. Basic Concepts Execute Cycle vary on op-code such as ADD R1, X will have 3 micro-operations t1 : MAR <--- (IR(address)) t2 : MBR <--- Memory t3 : R1 <--- (R1) + (MBR)

26. Basic Concepts Execute Cycle as ISZ X (Increment and Skip instruction) t1 : MAR <--- (IR(address)) t2 : MBR <--- Memory t3 : MBR <--- (MBR) + 1 t4 : Memory <--- (MBR)If ((MBR) = 0) then (PC <--- (PC)+1)

27. Basic Concepts Execute Cycle as BSA X (subroutine call : Branch-and-save-address instruction) t1 : MAR <--- (IR(address)) MBR <--- (PC) t2 : PC <--- (IR(address)) Memory <--- (MBR) t3 : PC <--- (PC) + 1

28. Basic Concepts Interrupt Cycle3 micro-operations t1 : MBR <--- (PC) t2 : MAR <--- Save_Address PC <--- Routine_Address t3 : Memory <--- (MBR)

29. Basic Concepts Each micro-instruction also explicitly or implicitly specifies the next micro-instruction to be used, thereby providing the necessary information for micro-operation sequencing. microprogram forms set of micro-instruction

30. Organization of Control Memory

31. Microinstruction Encoding

32. Microinstruction Encoding

33. Basic Concepts AdvantageMicroprogram can be changed relatively easily by changing the contents of CM. (flexible) DisadvantageThe time required to access the microinstructions from CM. Chip area and circuit delay must both be minimized. Used in CISC’s as the Pentium and MC680X0

34. Micro-instructions • Horizontal Formats long formats, little encoding of the control fields, and the ability to control many micro-operation in parallel. • Vertical Formats short formats, considerable control-field encoding, and limited parallelism. interpreted by nano-instruction that directly control the hardware.

36. Micro-instruction Types • Each micro-instruction specifies single (or few) micro-operations to be performed • (vertical micro-programming) • Each micro-instruction specifies many different micro-operations to be performed in parallel • (horizontal micro-programming)

37. Vertical Micro-programming • Width is narrow • n control signals encoded into log2 n bits • Limited ability to express parallelism • Considerable encoding of control information requires external memory word decoder to identify the exact control line being manipulated

38. Horizontal Micro-programming • Wide memory word • High degree of parallel operations possible • Little encoding of control information

39. Alternative Microinstruction Formats for a Simple Machine

40. Alternative Microinstruction Formats for a Simple Machine

41. Next Address Decision • Depending on ALU flags and control buffer register • Get next instruction • Add 1 to control address register • Jump to new routine based on jump microinstruction • Load address field of control buffer register into control address register • Jump to machine instruction routine • Load control address register based on opcode in IR

42. Functioning of Microprogrammed Control Unit

43. Design Considerations • Size of microinstructions • Address generation time • Determined by instruction register • Once per cycle, after instruction is fetched • Next sequential address • Common in most designed • Branches • Both conditional and unconditional

44. Sequencing Techniques • Based on current microinstruction, condition flags, contents of IR, control memory address must be generated • Based on format of address information • Two address fields • Single address field • Variable format

45. Branch Control Logic: Two Address Fields

46. Branch ControlLogic: Single Address Field

47. Branch Control Logic: Variable Format

48. Address Generation

49. Execution • The cycle is the basic event • Each cycle is made up of two events • Fetch • Determined by generation of microinstruction address • Execute

50. Execute • Effect is to generate control signals • Some control points internal to processor • Rest go to external control bus or other interface