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Design and Layout Guidelines

Design and Layout Guidelines. Robert Benjamin Applications Engineer benjamin_bob@ti.com. Information Sources. Information Sources. King Solomon: Book of Proverbs 15:22 Plans go wrong for lack of advice; many advisers bring success. 15:31

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Design and Layout Guidelines

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  1. Design and Layout Guidelines Robert Benjamin Applications Engineer benjamin_bob@ti.com

  2. Information Sources

  3. Information Sources King Solomon: Book of Proverbs • 15:22 Plans go wrong for lack of advice; many advisers bring success. • 15:31 If you listen to constructive criticism you will be at home among the wise.

  4. Information Sources • Internet/Magazines (Printed Circuit Design and Fabrication) • Trade Organizations (IPC, JEDEC, IEEE, SMTA) • TI Internal Sites • http://pwrmkt.itg.ti.com/DesignTools.htm • Your Neighbor

  5. Interference

  6. Interference • RFI • Phones (Cell and Home) • Broadcast Stations • Wireless Technologies (Computers, Blu-Tooth, Tablets) • EMI • Motors • Electrical Equipment • Power Sources (Man Made and Natural) • ESD • Crosstalk and Feedback

  7. Circuit Issues

  8. Key Circuit Issues • Drift • Linearity • EMI/RFI Protection • Component Selection

  9. DC drift Every component is a potential drift source; but the reference usually out-drifts them all! Parasitic thermocouples can also cause drift – watch out!

  10. In-circuit Thermocouples

  11. DC linearity Keep reference impedance low C0G caps if possible Consider driving differentially – also improves dynamic range Keep front-end balanced

  12. EMI/RFI Protection • Inductors – Ferrites, Coils • Capacitive Filters – Feed-Thru, X2Y • Warning: • Adding inductance to/through the ground connections will create more problems than it solves. Do NOT bridge Analog and Digital grounds with an inductor.

  13. External ESD Protection • A Need May Arise for Extra ESD Protection • Schottky Diodes. • Transient Voltage Suppression (TVS). • ESD Protection Device ICs (TPD4E001.)

  14. Moving from Circuit to Layout

  15. Capacitor Selection • Different Tasks Require Different Caps • Bulk (Tantalum, MLCC) • Bypass/Filter (MLCC-C0G, X2Y, X7R) • Signal Path (Mica, PPS, Film, MLCC-C0G)

  16. Signal Paths Require Quality CapsTHD+N vs. Voltage for Various Capacitor Types

  17. Shorter current path, Smaller current loops Dual parallel current paths to ground reduce inductance Opposing current flow reduces mutual inductance by cancellation. The structure is balanced, resulting in exceptional common mode filtering. X2Y is typically 1/10th the inductance of a like-sized conventional MLCC. Unlike MLCCs, inductance does not increase with size. The X2Y Advantage

  18. PCB Layout Tips

  19. Basic PCB Design Principles • Separate Analog and Digital Signals • Pay Close Attention on Connecting AGND and DGND • Provide Good Ground Return Paths • High Frequency Bypassing • Minimize Inductance (Vital for HS) • Control Thermocouples • Fill void areas on signal layers with ground fill. • Taking care of these things will also help improve EMI/RFI performance.

  20. Traces

  21. Board Traces • Traces Can Act Like Antennas • Traces Have Transmission Line Properties • Inductance • Resistance • Traces for Power Should be Wide • Connect and Terminate Effectively (vias)

  22. Source Signal Return Current Return Currents Digital Analog

  23. Loop Inductance

  24. 1 inch (7 mil) trace of 1/2 oz copper with 10μA of current => voltage drop of 1.3μV 4 LSBs (298nV) at 24 bits! PCB Layout TipsHigh Resolution Measurements 1 inch 1.3µV 10µA

  25. PCB Traces • Resistive AND Inductive • 1 inch 0.5 cm trace • Resistance = 0.0025 ohms • Inductance = 20 nH • Current change of 100 mA in 30 nS • Resistive Voltage of 250 uV • Inductive Voltage of 70 mV

  26. PCB Traces and Caps • Example – Reference Circuit (REF50xx or Buffered by OPA350) • Schematic • Layout • Rings @ 1/(2p (L * (C4*C5/(C4+C5)))1/2 ) = 3.58MHz

  27. PCB Layout Process • Review the Schematic and Mark Sensitive Areas • Sensitive Analog Paths • EMI and Other Interference Sources • Heat Sources • Consider External Connections • Spend Considerable Effort In Planning (Part Placement and Desired Routing Paths) • Prioritize the Analog Portion • Power Routing and Planes • Bypass Caps and Other Critical Components • Different Packaging Alternatives

  28. General Rules • Parallel Components Can Electromagnetically Couple • Traces Side to Side and Side by Side Can Couple • Consider Thru-Hole Interaction • Do Not Route Sensitive Nodes Through Components • Surface Mount Has Less Inductance, But Remember the Path (Vias)

  29. Component Rules • Keep Analog Signal Paths Short • Keep Inputs Away From Unwanted Outputs • Feedback • Oscillation • Maintain Effective Ground Plane • Keep Analog and Digital Portions Separate • Power Entry Better Near the Outputs • Keep Inputs and Outputs Separate • With Multiple Circuits Use Mirror Images • Planes and Shielding May Be Appropriate

  30. Bypass Capacitors • DO NOT have vias between bypass caps and active device – Visualize the high frequency current flow !!! • Ensure Bypass caps are on same layer as active component for best results. • Route vias into the bypass caps and then into the active component. • The more vias the better. • The wider the traces the better. • The closer the better. • X2Y may be a better choice. Poor Bypassing Good Bypassing

  31. Keep Analog I/O symmetrical Avoid putting heat sources near the Analog I/O Route Digital signals AWAY from the Analog signals Starting the Layout Analog I/O

  32. Partition the board into Analog and Digital sections when the layout permits. Split the ground plane if needed – but don’t if you don’t have to! Split or Solid? Analog Digital

  33. Keeping ground traces short: minimizes inductance reduces voltage differential between the board and chip substrate improves noise immunity Digital Grounding Analog Ground Pin

  34. Visualize Power Currents

  35. Current Reference Design

  36. The ADS1232REF

  37. ADS1232REF Layout: Top

  38. ADS1232REF Layout: Bottom Power Digital Analog

  39. New Reference Designs and Tests

  40. Schematic • Signal path • RC filter, Ferrite bead, Schottky Diode Array RC filter with cut off frequency is about 36Hz(differential signal) • Schottky Diode • Reverse Current 100nA (Max) • 100nA*2*1K*2%= 4uV(Worst case) • Only half of 1LSB(9.54uV) • Due to the symmetry of signal path, the • Reverse Current can be neglected Ferrite bead for input RF filtering Schottky Diode (Reverse Current 100nA)

  41. Schematic • Analog and digital power • Analog and digital power are isolated with L1(100uH) inductor

  42. Schematic Series input resistance to limit current flow to analog inputs and supply pins All decoupling Cap C4,C8,C9,C10 are as close as possible to the decoupling points

  43. PCB Layout (Through-Hole)

  44. PCB Layout (Thru-Hole) • One ground for both Analog and digital Analog power A chassis “ground ring” Digital power In order to save PCB size and for good layout, flying wire is used over top layer to provide analog power supply

  45. PCB Layout (SMD) • Ground Plane on Bottom-side Filter: R=1Kohm,C3=2.2uf, C1,C2=0.22uf, 2 Beads

  46. Layout Benefits • A chassis “ground ring” --additional EMI/RFI Filter components

  47. Customer Layout Issues Electronic Control Box +5VD +5VA C CM +5VA +5VD 0.22uF R W 1k FILT C Microcontroller DIFF ADC1230 Bridge R W 1k FILT 2.2uF Sensor C CM 0.22uF C PARASITIC C PARASITIC EMI Current Through ICs  Upset Large Loop Areas V EMI Undefined EMI Current Paths

  48. Improved Layout Electronic Control Box CX1 CX3 m m 0.01 F 0.01 F 1kV 1kV Defined EMI Current Paths +5VD +5VA C +5VA CM +5VD 0.22uF R W 1k FILT C Microcontroller ADC1230 DIFF Bridge R W 1k FILT 2.2uF Sensor C CM 0.22uF NO EMI Current Through ICs  NO Upset CX4 CX2 m 0.01 F m 0.01 F 1kV 1kV RX 1M 1kV Small Loop Areas V EMI EMI Currents seek path of least impedance. Analyze EMI path relative to chassis ground.

  49. Customer PCB Examples

  50. Customer Example

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