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Microelectronics 2

Electrical Engineering 2. Lecture 15. Microelectronics 2. Dr. Peter Ewen. (Room G08, SMC; email - pjse). Locus of V DS =V GS –V T. 20 16 12 8 4 0. 4. V GS = 10V 9V 8V 7V 6V 5V 4V 3V 2V. I D / mA. 2. 1. Fig. 89. gate. 3. W. source. drain. L.

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Microelectronics 2

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  1. Electrical Engineering 2 Lecture 15 Microelectronics 2 Dr. Peter Ewen (Room G08, SMC; email - pjse)

  2. Locus of VDS=VGS–VT 20 16 12 8 4 0 4 VGS = 10V 9V 8V 7V 6V 5V 4V 3V 2V ID / mA 2 1 Fig. 89 gate 3 W source drain L 0 2 4 6 8 10 12 14 16 18 20 VDS / volts PRE-SATURATION REGION 1. • Co – gate capacitance • per unit area (i.e. Cg/A) •  – mobility of majority • carriers in the channel • region The DRAIN-CURRENT EQUATION

  3. Note • ID→ IDS for saturation current • Saturation for MOS devices is entirely different from saturation for BJT’s Locus of VDS=VGS–VT 20 16 12 8 4 0 4 VGS = 10V 9V 8V 7V 6V 5V 4V 3V 2V ID / mA 2 1 3 0 2 4 6 8 10 12 14 16 18 20 VDS / volts SATURATION REGION 2. For VDS≥ VGS – VT pinch-off occurs and current saturates (at the value of ID when VDS = VGS – VT):

  4. Locus of VDS=VGS–VT 20 16 12 8 4 0 4 VGS = 10V 9V 8V 7V 6V 5V 4V 3V 2V ID / mA 2 1 In region 3 ID VDS The characteristics are linear and their slope depends on VGS – the device acts as a voltage-controlled resistor. 3 0 2 4 6 8 10 12 14 16 18 20 VDS / volts VOLTAGE-CONTROLLED RESISTANCE REGION 3. If VDS << VGS - VT

  5. Locus of VDS=VGS–VT 20 16 12 8 4 0 4 VGS = 10V 9V 8V 7V 6V 5V 4V 3V 2V ID / mA 2 1 3 0 2 4 6 8 10 12 14 16 18 20 VDS / volts BREAKDOWN REGION 4. For large VDS, avalanche breakdown occurs at the drain end of the device. +VGS Source +VDS Drain SiO2 n+ n+ p-type substrate

  6. MOS TRANSFER CHARACTERISTICS ID p-channel enhancement VT VGS 0 ID ID n-channel depletion p-channel depletion VT VGS VT VGS 0 0 Fig. 91 ID(VGS) for fixed value of VDS ID n-channel enhancement VT VGS 0 IDSS IDSS

  7. Locus of VDS=VGS–VT 20 16 12 8 4 0 4 VGS = 10V 9V 8V 7V 6V 5V 4V 3V 2V ID / mA 2 1 gm is usually (but not always) evaluated in the saturation region, so ID→ IDS 3 0 2 4 6 8 10 12 14 16 18 20 VDS / volts VDS = constant • gm depends on geometry and processing conditions • gm influences gain: • AV = -gmRL

  8. LECTURE 15  MOS Biasing Voltage-divider bias design • MOS Digital Circuits NMOS and CMOS • Comparison of MOS and bipolar transistors

  9. Voltage-Divider Bias Scheme Fig. 92(a) +VDD R1 RD ID drain n-channel enhancement gate source VGS Quiescent point (operating point) is stable against variations in device parameters VG IDRS R2 RS

  10. Drain Bias Scheme Fig. 92(b) +VDD IG~ 10-12 A  IG≈ 0 Hence VDS = VGS RD RG VDS > VGS – VT (if VT +ve) or VDS < VGS – VT (if VT -ve) ID IG drain gate VDS So an enhancement MOSFET is in saturation region of characteristics: source VGS

  11. Drain Bias Scheme Fig. 92(b) +VDD • Method for determining VT: √ID RD RG ID IG VDS (=VGS) VT VDS VGS VGS = VDS • MOSFET can be used as a (non-linear) resistor: R = VDS/IDS ; IDS~ VDS2

  12. IC resistors Iout Iin n-type region Region produced by implantation or diffusion of dopant p-type wafer View from above (high-value resistor) Cross section of a simple resistor Because semiconductor materials have a relatively low resistivity, large-value IC resistors require a long track length and so take up a lot of area on the chip.

  13. Source Bias Scheme Fig. 92(c) VDD • Q-point is stable RD • Can only be used for depletion MOSFETS • (e.g. n-channel enhancement device requires +ve VGS) ID D gate S VGS RG IDRS RS VG=0

  14. Source Bias with RS=0 20 16 12 8 4 0 VDD/RD VGS = +2.0V +1.5V +1.0V +0.5V 0V -0.5V -1.0V -1.5V -2.0V ID / mA Q-point VDD 0 2 4 6 8 10 VDS / volts Fig. 92(d) +VDD • Q-point is NOT stabilised (since • VGS is fixed) RD Load line is ID = (VDD–VDS) / RD • Because VGS=0, Q-point is automatically located in the middle of the output characteristics: ID D gate S VGS=0 RG

  15. VGSQ IDQ 20 16 12 8 4 0 VDD/(RS+RD) ID / mA VDSQ Q-point VDD 0 2 4 6 8 10 VDS / volts Designing the Voltage-Divider Bias Scheme VDD 1. Select the operating point (Q-point): IDQ, VDSQ,VGSQ R1 RD IDQ 2. Choose a value for VG which minimises the variation in IDQ due to variations in device parameters. gate VDSQ IDQ VGSQ VG R2 RS 3. Calculate RS: Fig. 92(a)

  16. Designing the Voltage-Divider Bias Scheme VDD 4. If VDD is known, calculate RD: R1 RD IDQ If RD is known, calculate VDD gate VDSQ IDQ VGSQ 5. Decide what the input impedance, Z, for the stage should be: VG R2 RS Fig. 92(a)

  17. VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Designing the Voltage-Divider Bias Scheme 6. Determine R1 and R2. VG is set by the voltage divider R1, R2: Hence: Fig. 92(a)

  18. VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Effect of VG Transfer Characteristic ID VG RS Bias Line slope -1/Rs 1 (VGSQ, IDQ) 3 Fig. 93(a) Fig. 93(b) 2 VGS VG VT Line gives large spread in IDQ 1 Line gives low spread in IDQ but also low average IDQ 2 Line gives low spread in IDQ and a reasonable average IDQ 3

  19. 5. Voltage-divider bias Determine resistor values for a voltage-divider bias scheme for an n-channel enhancement MOS amplifier with input impedance 15 MΩ, VDD = 18V and with the following quiescent values: IDQ = 2 mA; VDSQ = 12.75 V; VGSQ = 4.75 V Assume VG = 5.75 V for stability against variation in device parameters.

  20. Designing the Voltage-Divider Bias Scheme VDD 1. Select the operating point (Q-point): IDQ, VDSQ,VGSQ R1 RD 5. Voltage-divider bias Determine resistor values for a voltage-divider bias scheme for an n-channel enhancement MOS amplifier with input impedance 15 MΩ, VDD = 18V and with the following quiescent values: IDQ = 2 mA; VDSQ = 12.75 V; VGSQ = 4.75 V Assume VG = 5.75 V for stability against variation in device parameters. IDQ 2. Choose a value for VG which minimises the variation in IDQ due to variations in device parameters. gate VDSQ IDQ VGSQ VG R2 RS 3. Calculate RS: Fig. 92(a)

  21. 5. Voltage-divider bias VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Fig. 92(a) VDD = 18V IDQ = 2 mA VDSQ = 12.75 V VGSQ = 4.75 V VG = 5.75 V Zin = 15 MΩ Step 3 from design scheme gives:

  22. Designing the Voltage-Divider Bias Scheme VDD 4. If VDD is known, calculate RD: 5. Voltage-divider bias Determine resistor values for a voltage-divider bias scheme for an n-channel enhancement MOS amplifier with input impedance 15 MΩ, VDD = 18V and with the following quiescent values: IDQ = 2 mA; VDSQ = 12.75 V; VGSQ = 4.75 V Assume VG = 5.75 V for stability against variation in device parameters. R1 RD IDQ If RD is known, calculate VDD gate VDSQ IDQ VGSQ 5. Decide what the input impedance, Z, for the stage should be: VG R2 RS Fig. 92(a)

  23. VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Fig. 92(a) VDD = 18V IDQ = 2 mA VDSQ = 12.75 V VGSQ = 4.75 V VG = 5.75 V Zin = 15 MΩ Step 4 from design scheme gives:

  24. Designing the Voltage-Divider Bias Scheme VDD 6. Determine R1 and R2. VG is set by the voltage divider R1, R2: R1 RD 5. Voltage-divider bias Determine resistor values for a voltage-divider bias scheme for an n-channel enhancement MOS amplifier with input impedance 15 MΩ, VDD = 18V and with the following quiescent values: IDQ = 2 mA; VDSQ = 12.75 V; VGSQ = 4.75 V Assume VG = 5.75 V for stability against variation in device parameters. IDQ gate VDSQ Hence: IDQ VGSQ VG R2 RS Fig. 92(a)

  25. VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Fig. 92(a) VDD = 18V IDQ = 2 mA VDSQ = 12.75 V VGSQ = 4.75 V VG = 5.75 V Zin = 15 MΩ Step 6 from design scheme gives:

  26. MOS Digital Circuits n n n VDD Fig. 94(a) Depletion mode load transistor (acts as resistor) n X=A.B.C.D output A B C D n NMOS NAND Gate inputs Any input low (0V)  output is high (VDD) All inputs high  output is low

  27. MOS Digital Circuits n n n n NMOS NOR Gate Fig. 94(b) VDD Depletion mode load transistor (acts as resistor) n X=A+B+C+D output inputs A B C D Any input high  output is low All inputs low  output is high

  28. Fig. 78: Changes in market share for different transistor technologies GaAs 1% 100 90 80 70 60 50 40 30 20 10 0 ECL 9% TTL Percentage of market Analogue bipolar % market share PMOS 85% NMOS CMOS BiCMOS 5% 1985 1990 1995 2005 Year

  29. COMPLEMENTARY MOS (CMOS) CIRCUITS Fig. 95(a) CMOS Inverter VDD ID S Vin high  n-MOS on p-MOS off Hence output is low p-channel enhancement G D Vin output input D Vin low  n-MOS off p-MOS on Hence output is high n-channel enhancement G S ID Because one transistor in the pair is always in the off state, ID is the leakage current for the off device and so is very small. Hence power dissipation is very small.

  30. CMOS Inverter Structure Fig. 95(b) Vin G G VDD Vout n+ n+ p+ p+ n-type p-type substrate n-channel MOSFET p-channel MOSFET

  31. 6. CMOS output voltage The transistors in a basic CMOS inverter each have the same leakage current of 10 A. If the n-channel device has VT = 1.5 V and CoW/L = 10-4 A/V2, determine the output voltage, Vo, for Vin = 10V.

  32. 6. CMOS output voltage off Vin = +10V on VDS ID=10μA • Vin = 10V  n-channel device is on (VGS = +10V) and p-channel device is off. • Note that the output voltage of the inverter in this situation is VDS for the n-channel device. • ID = 10μA, so VDS will be very small and we must be operating in the voltage-controlled resistance region of the output characteristics:

  33. ID = 10 A CoW/L = 10-4 A/V2 Vin = VGS = 10V VT = 1.5 V This illustrates another advantage of CMOS – the output voltage is always close to one of the supply voltages and so is well defined.

  34. COMPARISON OF MOSFET’s AND BJT’s

  35. VDD R1 RD IDQ gate VDSQ IDQ VGSQ VG R2 RS Summary • MOSFET BIASING • Voltage-divider bias – gives stability against temperature/device variations • Design method – once Q-point, Zin, VDD and VG have been chosen, resistor values can be deduced.

  36. Drain bias – automatically puts an enhancement MOSFET in the saturation region of operation.  Can be used to measure VT  Enables MOSFET to be used as a resistor • Source bias – can only be used for depletion mode devices.

  37. MOSFET DIGITAL CIRCUITS • n-channel devices can be combined to realise logic gates (p-channel gates are slower) • CMOS circuits use both n- and p-channel devices  CMOS circuits are very important because of their very low power consumption.  In n-well technology p-channel devices are made in an n-type “well” or “tub”

  38. Advantages of MOSFET’s over BJT’s Smaller Easier to make Very low power consumption But Slower operation

  39. Class Test • Lecture 17 - Monday Week 9 (12th November) • 30 minutes, starting at 12.10pm • 7 or 8 “Section A” type questions • Covering the material in the first and second handouts (basic semiconductor theory, IC fabrication, pn junction diodes) • Formula sheet will be provided

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