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J. Panman CERN VLVNT workshop 7 Oct 2003. DAQ: comparison with an LHC experiment. Use as example CMS (slides taken from Cittolin's talk at LHCC) Take numbers floating around this week as typical performance needs. Data source: sampling frequency 200- 400 Mhz sampling precision 8 bits
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J. Panman CERN VLVNT workshop 7 Oct 2003 DAQ: comparison with an LHC experiment Use as example CMS (slides taken from Cittolin's talk at LHCC) Take numbers floating around this week as typical performance needs
Data source: sampling frequency 200-400 Mhz sampling precision 8 bits sample length 50-100 ns No. OMs 10000 No. towers/strings 400 Background rate 50-200 kHz/OM Data to shore: links per tower/string 1 data rate/link 1.6 Gbits/s total data rate 640 Gbits/s Event organization: “Event” window length 10 ms size of data/event 800 Mb Comparison of design parameters Take numbers floating around this week as typical performance needs For simplicity: use a “digitized scenario” (waveforms transmitted)
Data source: sampling frequency 200-400 Mhz sampling precision 8 bits sample length 50-100 ns No. OMs 10000 No. towers/strings 400 Background rate 50-200 kHz/OM Data to surface: Average event size 1 Mbyte No. FED S-link64 ports 700 DAQ links (2.5 Gb/s) 512+512 Event fragment size 2 kB FED builders (8x8 dual) 64 Technology(2004) Myrinet Data to shore: links per tower/string 1 data rate/link 1.6 Gbits/s total data rate 640 Gbits/s Total data rate: total data rate 800 Gbits/s Event organization: “Event” window length 10 ms size of data/event 800 Mb Comparison of design parameters Take numbers floating around this week as typical performance needs For simplicity: use a “digitized scenario” (waveforms transmitted) CMS
Credits slides taken from Cittolin's talk at LHCC
1990' PCI Desktop/Server GByte memory MultiProcessor current architecture Peripheral IO bus PCI: MEM 264 MB/s 33/66 MHz x 32/64 bit Pxx Pxx SIO 100/200/400 MB/s Pxx PCI Dual PCI Pxx MEM PCI Pxx Pxx 264 MB/s Pxx Pxx Front end Readout network FE digitizer Data from a string Data from a string DSP-like operation: filter produces time&charge from waveform assume 8 bytes to encode (reduction x3) 200X: PCI-X …
Network configurations FED -> FE digitizer EVB staging by switch expansion: EVB staging by switch expansion:
FED Builder (64 units) 8x8 x 5 Gb/s switch Event fragments merger Readout Builder (up to 8) 64x64 x 2.5 Gb/s switch Event rate 12.5 kHz CMS – 2 stages: Data to surface & Readout Builder Data to surface (rate decimation) 2 kByte 16 kByte
FED Builders Programmed to send events to two output (odd and even EvNo.) CMS – DAQ staging : 2 RBs = 25 kHz Data to surface (rate decimation) Readout Builders (modular staging)
CMS – DAQ staging : 8 RBs = 100 kHz Data to surface (rate decimation) Readout Builders (modular staging)
CMS – 3-D DAQ implementations and scaling Data to surface: Average event size 1 Mbyte No. FED S-link64 ports 700 DAQ links (2.5 Gb/s) 512+512 Event fragment size 2 kB FED builders (8x8 dual) 64 Technology(2004) Myrinet Readout Builders (x8): Lv-1 max. trigger rate 12.5 kHz RU Builder (64x64) .125 Tbit/s Event fragment size 16 kB RU/BU systems 64 Event filter power 105 SI95 EVB technology (2006) Open
Comparison of numbers Total data rate of km3 detector similar to an LHC detector after the L1 trigger Number of data sources similar to number of FE Digitizers Waveform filtering (if possible) reduces the data volume by factor 3 Moore's law will help by factor 4-8 compared to LHC Output rate of HLT farm in km3 (presumably) much lower than 100 Hzx1Mb Probably data storage problem much smaller than LHC HLT processing time/byte looks to be smaller than at LHC (LHC has to reject real physics events)
Summary DAQ architecture of LHC experiments can be a useful starting point for a design Similar techniques, but probably smaller requirements A couple of years later: profit from experience profit from performance/price ratio trend At a first glance the DAQ does look feasable