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AFEII update Juan Estrada

AFEII update Juan Estrada. I am now looking at details of the analog readout of the TriP chip, for this reason the presentation will be heavily concentrated on that aspect of the project. Plans. electrical problem. Our Board. MCMIIc (32ch.). MCMIIb (64ch.). MCMIIb. FPGA. JTAG cable

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AFEII update Juan Estrada

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  1. AFEII update Juan Estrada • I am now looking at details of the analog readout of the TriP chip, for this reason the presentation will be heavily concentrated on that aspect of the project. • Plans

  2. electrical problem Our Board MCMIIc (32ch.) MCMIIb (64ch.)

  3. MCMIIb FPGA JTAG cable (temporary solution) 2 ADCs DIGITAL ANALOG 2 TriP chips inside Charge injection connector

  4. Analog readout work for the TriP • The TriP chip has an analog pipeline (same as the SVX) • The output (~10mV/fC) of the pipeline is read sequentially, in two MUXs (each for 16 channels). • The outputs of the MUXs are digitized in a dual ADC (commercial part outside the TriP). • The Output of the ADC goes into the memory of the FPGA that combines it with the trigger information and sends it to the Sequencer. (all the steps are controlled by the FPGA)

  5. Analog Readout of the TriP Chip MODE lines to FPGA ACQUIRE ADC CLK PR1 MUX CLK ANALOG OUT from TRIP 2 4 6 8 10 ADC BIT to FPGA

  6. Noise in the analog readout 10 fC signal ~ 100 mV 25 mV width

  7. So far good…but • The problem is that we are trying a modification in the FPGA code and the analog readout stops working… we are trying to see where is the bug.

  8. What do we have? • We have installed 4 MCMs in the board (1 of them needs some work before we can use it). 5 working TriP chips. • We have implemented an interface to download and read the TriP registers (pipeline, gain, etc…) using 1553. • We have a working version of the FPGA code for MCMIIb and MCMIIc, but this version requires download of new firmware for every change in the TriP clocks. We are working on a new version where we can change the clocks using the 1553 interface (this will be very convenient for our tests, not for real operation).

  9. Plan for few months • Characterization of 32x5 channels in WH14 • Move to DAB to use the 4 cassettes cryostat • Implement the FPGA programming using the a special board the Bruce and Ivan designed for this purpose, parts are here. • We expect the packages chips soon (3 weeks), we have to characterize it (this is important for a final decision on the packaging). We have an MCMIIc with all the parts waiting for the packaged Trip.

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