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FPGA Tools Course Timing Analyzer

FPGA Tools Course Timing Analyzer. Objectives. Understand how the Timing Analyzer enables users to determine their design performance Describe Timing Report options Explain how choosing a different Timing Report can provide different information Learn how to verify your design’s performance.

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FPGA Tools Course Timing Analyzer

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  1. FPGA Tools CourseTiming Analyzer

  2. Objectives • Understand how the Timing Analyzer enables users to determine their design performance • Describe Timing Report options • Explain how choosing a different Timing Report can provide different information • Learn how to verify your design’s performance

  3. Outline • Using the Timing Analyzer • Understanding the Timing Analyzer Reports • Summary

  4. Invoking the Timing Analyzer • Alliance users: Select the Timing Analyzer icon in the Design Manager window • Foundation users: Select Start -> Products -> Xilinx Foundation Series -> Accessories -> Design Manager -> Timing Analyzer

  5. Understanding the Timing Analyzer • The Timing Analyzer views the design in terms of pads and synchronous elements • Hard nodes • Synchronous elements are Registers, Rams, and Latches. • The Timing Analyzer will calculate the delays for paths that travel from input pads and synchronous elements to output pads and synchronous elements. • All Timing Analyzer reports use this information and can report it in several different formats. • All delays are worst case.

  6. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN How Many Paths? com com • How many pad-to-pad delay paths are in this design? • How many pad-to-synchronous element paths? • How many synchronous-to-synchronous element paths? • How many synchronous-to-pad paths? • How many paths would a PERIOD constraint cover? • How many paths would an OFFSET IN constraint cover? • How many paths would an OFFSET OUT constraint cover?

  7. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN How Many Paths? com com • How many pad-to-pad delay paths are in this design? 1 • How many pad-to-synchronous element paths? 2 • How many synchronous-to-synchronous element paths? 1 • How many synchronous-to-pad paths? 3 • How many paths would a PERIOD constraint minimize? 3 • How many paths would an OFFSET IN constraint minimize? 2 • How many paths would an OFFSET OUT constraint minimize? 3

  8. Five Types of Timing Analyzer Reports • The Report Paths in Timing Constraints report compares the design’s performance to the timing constraints. • Each constraint will be listed with its longest delay path broken down by delay type (i.e. net and logic). • The Report Paths Failing Timing Constraints report lists only the paths that do not meet the timing constraints. • Each failing constraint will be listed with its longest delay path and show by how much the constraint was missed. • The Report Paths Not Covered by Timing Constraints lists all paths in the design and their corresponding delay. • This report lists all unconstrained and constrained paths in the design.

  9. Five Types of Timing Analyzer Reports • The Advanced Design report provides a set of summary statistics. • This is essentially an error report that displays a summary header for each constraint whether it passes or not and lists paths in error for constraints that are violated. • If no constraints are specified, this report displays the maximum clock frequencies for all clocks in the design and the worst-case timing for all clock paths. • The Custom report contains a detailed analysis of all specified paths in the design. • This report is customized by selecting sources, destinations, or paths with the Path Filters command. • If nothing is selected for customizing the report, all paths in the design will be analyzed, and the longest delay path will be reported.

  10. General Recommendations • If you care about the Maximum Clock Frequency, enter a Period constraint with the design. • This will make the Advanced Design report confirm the Maximum Clock Frequency, and guarantee design performance. • If no Period constraint is used and other constraints are used, the Advanced Design report displays the Maximum path delay to/from any node, which is the longest delay path in the design. • The number of paths listed by any of these reports can be controlled by using the command: • Options->Report Options

  11. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN What kind of report should be used to analyze this design? com com • Constraints Editor: Period = 50ns; Offset Out = 50ns After CLK; • Which report will show the maximum clock frequency? • Which report will show the longest delay path minimized by a PERIOD constraint? • Which report will show the delay from CIN to OUT2?

  12. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN What kind of report should be used to analyze this design? com com • Which report will show the maximum clock frequency? • Any of the Timing Analyzers reports • Which report will show the longest delay path minimized by a PERIOD constraint? • Report Paths in Timing Constraints report • Which report will show the delay from CIN to OUT2? • Since there is no constraint on this path, the Report Paths Not Covered by Timing Constraints report.

  13. What is Performance? • Performance typically refers to maximum clock frequency, not maximum system clock frequency. • In other words, the Maximum Frequency reported by Timing Analyzer uses the longest delay path from a synchronous element to another synchronous element in its calculation. • The Maximum System Clock Frequency is dependent upon the board delays, setup and hold times of external devices, and clock skew. • By using the necessary timing constraints, you can create your own definition of FPGA performance.

  14. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN What is Performance? com com • If the longest pad to synchronous element delay is 10 ns, the longest synchronous-to-synchronous element delay is 15 ns, and the longest synchronous-to-pad delay is 20 ns, what is the Maximum Frequency reported by the Timing Analyzer? • With these same conditions, what is the Maximum System Clock Frequency?

  15. FLOP FLOP D Q D Q AiN OUT1 CLK FLOP BUFG BiN D Q OUT2 CiN What is Performance? com com • If the longest pad to synchronous element delay is 10 ns, the longest synchronous-to-synchronous element delay is 15 ns, and the longest synchronous-to-pad delay is 20 ns, what is the Maximum Frequency reported by the Timing Analyzer? • 1/15ns = 66.7 Mhz • With these same conditions, what is the Maximum System Clock Frequency? Worst of... • 1/(10ns + upstream device delay{clock2out + trace delay + clock skew}) • 1/(20ns + downstream device delay{setup time + trace delay + clock skew})

  16. Outline • Using the Timing Analyzer • Understanding Timing Analyzer Reports • Summary

  17. Report Options • These options allow the user to modify the appearances of each of the Timing Analyzer reports. • Summary Report Only • This format lists the longest delay path and the number of failing paths. • Limit Report To: • This allows the user to quickly change the number of paths that are displayed by the Timing Analyzer reports.

  18. Selecting Specific Paths • Use the Select Sources and Select Destinations options to report the delays of specific paths in a project. • Sources and destinations can be: • Flip-Flops, RAMs, Latches, Pads, Nets, Pins, CLBs, and Clocks • Speed Grade option helps the user determine if they need a faster device, or if they can use a slower speed grade.

  19. Report Example • Lists Constraint • Total number of paths analyzed • Maximum delay path • Hierarchical path description • Detailed path description • Delay Types found in Data Book • Worst-case delay values • Total delay • Percentage breakdown

  20. Report Example • TimeGroup Sources • TimeGroup Destinations • Timing Errors informs if all constraints were met • Maximum Frequency • Maximum path delay from/to any node

  21. Outline • Using the Timing Analyzer • Understanding the Timing Analyzer Reports • Summary

  22. Summary • The Timing Analyzer breaks down each design in terms of pads and synchronous elements when analyzing design performance. • Maximum Frequency, as reported by the Timing Analyzer, is different from Maximum System Clock Frequency. • Use the Report Paths Not Covered by Constraints option to check for unconstrained paths. • Select specific paths to get detailed timing information.

  23. Questions • How do you determine what the longest delay path is in your design? • How can you be certain that all timing constraints were met? • If a PERIOD constraint of 20 ns is specified and you find a maximum delay path from any node/to any node of 30 ns, could all of the constraints have been met?

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