Leakage reduction techniques

1. Leakage reduction techniques Mohammad Sharifkhani

2. Introduction • Leakage current is important in • Standby mode: no T. activity • Active mode: Static units: (e.g., SRAM cells) • Active mode: Non-critical path logics • It is the current that does not do anything for us The lower the better

3. Power components (revisit) • Speed • Energy  Battery lifetime • Instantaneous power  Package, cooling The leakage power is a function of Vth, VDD and transistor size.

10. Power Down • Complexity: • Cellular phone: checks base-station every sec. in cell waiting mode partitioning the design

12. Floating output nodes between 0.7V/0 • High leakage in subsequent stage  pull-downer  area, power

13. Power Down • 100uSec settle time for power up. Windows-CE demands 1uSec • On board level: • Turn off: All input signals to a chip  0; otherwise short through ESD. Then turn off chip VDD • Turn on: Reverse order. Except for the active low inputs which may disrupt the operation (e.g., CE, OE) • Un-conventional power up/down methodology

14. Power Down • High Vth Sleep T. • Multi-Threshold MTCMOS • Both VDD and Virtual VDD  Area • Sizing Sleep T.: • Speed: virtual VDD bounce  Large enough • Discharge pattern  virtual VDD bounce  Delay • VDD↓  Larger W/L; @ VDD=0.7 super cut-off T. SCCMOS

15. Power Down • Example Input Pattern: 8x8 Multiplier speed penalty <5% • Second pattern  W/L=60, First pattern  W/L=170 • Right pattern is hard to find • In consistent with conventional CMOS design

16. Power Down • High Vt Sleep T. • Does not operate at Vdd<0.7V • Super cut-off transistor (SCCMOS) • Instead of high-Vt transistor, a regular transistors is used for Sleep T. • The gate of the Sleep T. is connected to Vdd+0.4V during cut-off • Operates at lower voltages (<0.7V)

20. Layout

21. Standard Cell implementation

22. Multiple Vt • Multiple Vt is a common standard today • It can be used in • Static CMOS • Domino • It can be used as • In block level (Sleep T.) • Circuit level

24. Dual Vt for Domino

25. Preserving State • Virtual supply collapse in sleep mode will cause the loss of state in registers • Putting the registers at nominal VDD would preserve the state • These registers leak • Can lower VDD in sleep • Some impact on robustness, noise and SEU immunity

26. Low-leakage FF w. Sleep High Vt

32. Stacking

33. Stacking

34. Stacking

43. 3 Challenges • High standby current in low Vth • IDDQ testing failure • Degradation of worst case speed due to Vth variation @ low Vth • Vth scaling to keep delay constant: for 3V => 2V change 25% Vth reduction is needed

44. Vth controlling • Solves all three problems together • Variable threshold CMOS (VTCMOS) • Can be used as a low-voltage (low active power) method • Two main blocks: • Leakage current monitor (LCM) • Self substrate bias (SSB) • Two major schemes: • Self-adjusting threshold voltage (SAT) • Standby Power Reduction (SPR)

45. VTCMOS • The body of the T. is the key controlling knob. • All properties of CMOS is carried over (unlike Power Down)  • Much smaller current flows through Substrate.  • Slow turn off, Fast turn on  • <0.1um Sec. good for Windows-CE

49. Self-Adjusting Threshold-Voltage Scheme (SATS)

50. SATS Experimental Results