Logical Protocol to Physical Design. Correctness: a cache-coherent memory system must satisfy the requirements of coherence. It should ensure that stale copies are found and invalidated or updated on writes, and it should provide write serialization.
Implementation must contend with
Minimal extra hardware
Figure1: a uniprocessor cache design
Let’s first see an atomic bus and a single-level cache design !!
Free of :
Tags and state used by processor
Tags and state used by Bus Snooper
When a state or a tag for a block is updated
Both tags need to be updated
Processor initiates transaction by placing address and command on the bus
Bus-side controller snoops on the cache tags and WB tags
Wired-OR signal: serve as acknowledgement to the initiator that all caches have seen the request and taken appropriate action
Suppose P1 and P2 attempt to write cached block A simultaneously
See example next slide.
Scenario: P1’s write will check its cache determines that it needs to change the state of the block from S->M before it can write data into the block, and issues an upgrade bus request (a BusUpgr: similar to BusRdX but does not cause memory or other caches to respond with the data for the block)
In the meantime, P2 has also issued a BusRdX for A, and it may have won bus arbitration for the bus first. P1’s controller will see the bus transaction and must downgrade the state of the block from S to I in its cache.
Otherwise, when P2’s transaction is over, A will be in modified state in P2 and in shared state in P1, which violates the protocol.
But now the upgrade bus request that has P1 outstanding is no longer appropriate and must be replaced with a Read-Exclusive request.
How do we implement this??
In response to a write operation to a
Block in the S state, the cache
1) Begins arbitration for the bus by issuing
2) And transitions to the intermediate
State S M.
The state transitions to M upon a busgrant.
However, if a BusRdX is observed then the
Controller treats the block as having been
Invalidated and transition to the I M state.