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Deterministic Approaches to Analog Performance Space Exploration (PSE)

Deterministic Approaches to Analog Performance Space Exploration (PSE). D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann. Institute of Electronic Design Automation, TU Muenchen, Munich , Germany. Outline. Introduction to Performance Space Exploration (PSE)

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Deterministic Approaches to Analog Performance Space Exploration (PSE)

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  1. Deterministic Approaches to AnalogPerformance Space Exploration (PSE) D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann Institute of Electronic Design Automation, TU Muenchen, Munich , Germany

  2. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  3. Motivation • Analog circuits in mixed-signal systems: • Signal conversion, clock generation, data acquisition, ... • Performance Space Exploration (PSE): • For given topology and technology of an analog circuit block determine its performance capabilities. • Applications: • Visualize Trade-Offs between competing performances • Compare topologies which implement same analog functionality • Topology selection • Bottom-up propagation of information about implementation capabilities in a hierarchical sizing process

  4. Methods • Extensive search: • Parameter sweep: p (CMOS: W,L) • Performances fobtainedby simulation • (high computational costs) OpAmp Feasible performance space F

  5. Methods • Extensive search: • Parameter sweep: p (CMOS: W,L) • Performances fobtainedby simulation • (high computational costs) • Two deterministic approaches DISC/POLY (see Paper for state-of-the-art) • What determines the Feasible Performance Space of a circuit block? • Sizing constraints OpAmp • More efficient determination? Feasible Performance Space F

  6. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  7. i1 i2 Sizing Constraints: Formalized design knowledge • Basic functional blocks: e. g. current mirror i2 = K i1 electrical geometrical function robustness

  8. i1 i2 Sizing Constraints: Formalized design knowledge • Basic functional blocks: e. g. current mirror Reduce effect of channel length modulation i2 = K i1 Saturation electrical geometrical Reduced Parameter set p function Sizing constraints c(p) ≥0 robustness Analog minimum feature size Robustness against local threshold voltage variations (mismatch)

  9. VDD Out VDD Ibias Out INn Inp Ibias INn INp VSS VSS Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp

  10. VDD Out VDD Ibias Out INn Inp Ibias INn INp VSS VSS Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. Current Mir. Load Current Mirror Level Shifter Differential Pair

  11. VDD Out VDD Ibias Out INn Inp Ibias INn INp VSS VSS Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. 4-T Current Mir. Current Mir. Load Current Mir. Bank Current Mirror Level Shifter Bank Level Shifter Cascode Cur. Mir. Differential Pair

  12. VDD Out VDD Ibias Out INn Inp Ibias INn INp VSS VSS Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. 4-T Current Mir. Current Mir. Load Current Mir. Bank Current Mirror Cas. Cur. Mir. Bank Level Shifter Bank Level Shifter Differential Stage Cascode Cur. Mir. Differential Pair

  13. VDD Out VDD Ibias Out INn Inp Ibias INn INp VSS VSS Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp 8 Design Parameters p 62 Sizing Constraints c(p)≥ 0 Voltage Ref. 11 Design Parameters p 181 Sizing Constraints c(p)≥ 0 4-T Current Mir. Current Mir. Load Current Mir. Bank Current Mirror Cas. Cur. Mir. Bank Level Shifter Bank Level Shifter Differential Stage Cascode Cur. Mir. Differential Pair

  14. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  15. PSE by discretized Pareto Fronts – DISC Feasible Performance Space Pareto Optimal Front for max f1, max f2 Utopia point

  16. Normal Boundary Intersection – DISC • Individual performance • optima

  17. Normal Boundary Intersection – DISC • Individual performance • optima 2.Convex hull, discretized

  18. Normal Boundary Intersection – DISC • Individual performance • optima 2.Convex hull, discretized 3.Line search perpendicular to convex hull

  19. Topology selection with DISC DC Gain > 75dB Phase Margin > 60o DC Gain > 75dB Phase Margin > 80o Folded–Cascode OpAmp Miller OpAmp Folded–Cascode OpAmp Miller OpAmp Folded–Cascode OpAmp Miller OpAmp

  20. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  21. Simulation P f=f(p) PSE by Polytopal Approximation - POLY  Nonlinear problem F k(f)≥0 c(p) ≥ 0

  22. Simulation P f=f(p) Linearisationatp0: Δp = p – p0 P Δf=FΔp PSE by Polytopal Approximation - POLY  Nonlinear problem F k(f)≥0 c(p) ≥ 0  Lineardescription F C Δp≥ c0 K Δf≥ k0 Linear Circuit Model Polytope Polytope

  23. Results POLY DC Gain > 75dB Phase Margin > 60o Folded–Cascode OpAmp Miller OpAmp

  24. Comparison POLY-DISC DC Gain > 75dB Phase Margin > 60o Folded–Cascode OpAmp Miller OpAmp

  25. Comparison POLY-DISC DC Gain > 75dB Phase Margin > 60o Folded–Cascode OpAmp Points of Linearisation Miller OpAmp

  26. Comparison POLY-DISC DC Gain > 75dB Phase Margin > 60o Folded–Cascode OpAmp Computational time on cluster of 15 Pentium IV Points of Linearisation ACCURATE FAST Miller OpAmp

  27. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  28. Flat Sizing Process System specification System performances (fc, Gc, Q) CIRCUIT LEVEL Circuit parameters (wMN1,lMN1,…) Circuit sizing

  29. Hierarchical Sizing Process System performances (fc, Gc, Q) System specification SYSTEM LEVEL System sizing System parameters (gm(OTA8), CT(OTA8),…) ↓ = Circuit specification Circuit performances (gm,φ(fc),…) CIRCUIT LEVEL Circuit parameters (wMN1,lMN1,…) Circuit sizing

  30. Hierarchical Sizing Process System specification WE NEED TO AVOID Resizing Loop SYSTEM LEVEL Feasible system parameters System level constraints System sizing Too ambitious system sizing ↓ ↓ ↑ Circuit specification Unrealistic circuit specifications Performance Space Exploration CIRCUIT LEVEL Circuit sizing can not meet specification Circuit sizing

  31. Hierarchical Sizing of OTA-C Filter Sizing without system constraints Sizing with system constraints Filter Spec. fc = 2 MHz; Gc≥ 20 dB; Q ≥ 15 SYSTEM LEVEL CIRCUIT LEVEL

  32. Hierarchical Sizing of OTA-C Filter Sizing without system constraints Sizing with system constraints Filter Spec. fc = 2 MHz; Gc≥ 20 dB; Q ≥ 15 SYSTEM LEVEL System level sizing System level sizing OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 Spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 Spec. gm = 299.7 μS Cin = 32.57 fF φ(fc) = 175.3 deg Rout = 229.4 MΩ Cout = 22.9 fF CIRCUIT LEVEL

  33. Hierarchical Sizing of OTA-C Filter Sizing without system constraints Sizing with system constraints Filter Spec. fc = 2 MHz; Gc≥ 20 dB; Q ≥ 15 SYSTEM LEVEL System level sizing System level sizing OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 Spec. gm = 205.1 μS Cin = 32.9 fF φ(fc) = 174.0 deg Rout = 184.4 MΩ Cout = 21.6 fF OTA 5 Spec. gm = 299.7 μS Cin = 32.57 fF φ(fc) = 175.3 deg Rout = 229.4 MΩ Cout = 22.9 fF CIRCUIT LEVEL Circuit level sizing Circuit level sizing

  34. Outline • Introduction to Performance Space Exploration (PSE) • Sizing constraints and structural circuit analysis • PSE by discretized Pareto Optimal Fronts (DISC) • PSE by Polytopal Approximations (POLY) • Application to hierarchical sizing • Conclusions

  35. POLY DISC FAST ACCURATE Conclusions Deterministic Performance Space Exploration Approaches based on sizing constraints Support designer in comparing different topologies for implementing a given analog functionality Provide information about underlying implementations on system level avoiding resizing loops

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