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Upgrading the Digital Component of the Bunch Current Monitors

Upgrading the Digital Component of the Bunch Current Monitors. Josh Kline Mentor: Alan Fisher. Where? What? Why?. The PEP II storage rings at the Stanford Linear Accelerator Center. The digital portion of the bunch current monitor interface system.

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Upgrading the Digital Component of the Bunch Current Monitors

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  1. Upgrading the Digital Component of the Bunch Current Monitors Josh Kline Mentor: Alan Fisher

  2. Where? What? Why? • The PEP II storage rings at the Stanford Linear Accelerator Center. • The digital portion of the bunch current monitor interface system. • The original components are from 1995 and have become difficult to replace.

  3. How the ring works • Electrons/positrons are fed to the ring from the linear accelerator. • The ring pushes bunches of electrons/positrons around the ring using microwave radiation. • Buckets are phases of the standing microwave that supplies the bunch with the energy equal to what it radiates.

  4. How the detectors work • The detector measures the electric field of a passing charge bunch. • The charge bunches are moving with relativistic speed, causing the electric field to flatten so the detector sees a fast pulse. v

  5. The analog electronics • The analog system turns the fast pulse of the bunch current detector into two periods of a sinusoid using a comb filter with a reference frequency of 1428 MHz the then signal goes through a low pass filter and is then digitized.

  6. BLOCK DIAGRAM Detector Current system Comb filter Digitizer Decimator 6 FPGAs Digital to Analog Digitizer Decimator 6 FPGAs Detector Proposed system Comb filter Digitizer FPGA Digital to analog Main control

  7. Big problem, some of the electronics have become to old to be replaced. Little problem, the system is too slow to handle the full data rate, so 7/8 of the data is thrown away. The current system

  8. The proposed system • Big solution, modern components. • Little solution, the new system is fast enough to sample at the full data rate.

  9. Linux computer One digitizer One FPGA One digital to analog I/O bus VXI crate processor Two Digitizers Two Decimators Twelve FPGAs One digital to analog I/O bus Details Proposed Current

  10. The First Step • Testing the prototype using software simulator, signal generator, and the last test will be connecting the prototype in parallel with the current system.

  11. ModelSim

  12. Test Bench

  13. Conclusion • The prototype has been simulated using ModelSim. • The prototype has been tested using a saw tooth signal generator. • The final test is yet to be preformed.

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