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Biscotti: a Framework for Token-Flow based Asynchronous Systems. Charlie Brej. Overview. The tool problem Proposed system Biscotti components Their current state Example uses Conclusions And future work. The Tool Problem. Wagging Flow Problem. Verilog Read. TLF Read. Netlist

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Presentation Transcript
overview
Overview
  • The tool problem
    • Proposed system
  • Biscotti components
    • Their current state
  • Example uses
  • Conclusions
    • And future work
wagging flow problem
Wagging Flow Problem

Verilog

Read

TLF

Read

Netlist

Flatten

Timing

Library

Async Trans.

Wag

Timing

Extract

Simulation

Performance

Async Trans.

Desynchronise

Netlist

Flatten

Verilog

Write

commercial tools
Commercial Tools
  • Unsuitable
    • Critical path extraction
  • Broken
    • Timing extraction of cyclic designs
  • Inflexible
    • Limited simulation trace extraction
  • Unimplemented
    • DI logic synthesis
biscotti aims
Biscotti Aims
  • Complete framework for token flow systems
    • Aims to recreate all tools required to make a design
  • Modular
    • Set of libraries
  • Open Source
    • GPLv3
  • Expandable and Customisable
    • Trivial to add or replace any part with own version
parts
Parts

Verilog

TLF

Netlist

Operations

Async Transformations

Simulation

Timing

Wagging

Tech-map

Verilog

SDF

input
Input

primitive trinary_C(Z,A,B);

output Z;

input A, B;

reg Z;

table

// A B : Z : Z’

0 0 : ? : 0;

1 1 : ? : 1;

2 2 : ? : 2;

? ? : ? : -;

endtable

endprimitive

  • Verilog
    • Modules, Gates
    • UDPs with MVL extensions
    • No behavioral
  • TLF
    • Cell characterisations
    • Splines
      • In: Capacitance and Slew
      • Out: Delay and Slew
output
Output
  • Verilog
    • Patchy
    • Generates verilog executable with NC-Verilog
  • SDF
    • Timing extraction files used by external simulators
processing 1
Processing 1
  • Netlist Operations
    • Internal netlist representation
      • Allows constructing, altering, flattening...
    • The basis of all other tools
  • Timing
    • Cell timing characteristics (TLF)
    • Circuit timing extraction
    • Characterisation of constructed modules
processing 2
Processing 2
  • Pipeline Synthesis
    • Takes a directed flow graph (DFG) style circuit
    • Constructs latches and acknowledge trees
    • Can expand to early output, DIMS or MVL
    • Creates RAM wrappers and wagging fork/join blocks
pipeline synthesis

C

Pipeline Synthesis

Async

Latch

Async

Latch

Logic

Async

Logic

Async

Latch

Async

Latch

Async

Latch

processing 21
Processing 2
  • Pipeline Synthesis
    • Takes a directed flow graph (DFG) style circuit
    • Constructs latches and acknowledge trees
    • Can expand to early output, DIMS or MVL
    • Creates RAM wrappers and wagging fork/join blocks
processing 3
Processing 3
  • Wagging
    • Duplicates circuit and reconnects latches to form a ring
    • Inserts abstract fork/join blocks
  • Simulation
    • Fast simulator
    • Slowest trace extraction
    • MVL capable
      • Allows simulation at an abstract level
processing 4
Processing 4
  • Tech mapping
    • Dumb generation of large primitives (balanced trees)
    • Table based re-synthesis of C-element blocks
      • Logic blocks in the future
    • Slowest trace based gate replacement (drive strength)
timing extraction
Timing extraction

Verilog

Read

TLF

Read

Netlist

Flatten

Timing

Extract

Verilog

Write

SDF

Write

extract slowest path
Extract Slowest Path

Verilog

Read

TLF

Read

Netlist

Flatten

Timing

Extract

Simulation

Slowest Trace

Slowest Path

Write

drive strength optimisation
Drive Strength Optimisation

Verilog

Read

TLF

Read

Verilog

Write

Netlist

Flatten

Timing

Extract

Simulation

Slowest Trace

Netlist

Replace Element

Tech-map

Find Better Cell

large c element generation
Large C-element generation

Verilog

Read

TLF

Read

Async Trans

C-element Gen

Timing

Extract

Tech-map

Find Better Cell

Timing

Generate Splines

Verilog

Write

TLF

Write

current state
Current state
  • Pre-alpha
    • Pretty unusable
  • Used to generate RedStar
    • Parts implemented when needed
  • About 6 months from public beta
    • Currently available on request
future work
Future Work
  • Implement RedStar using system
    • Using as few commercial tools as possible
    • Example design
  • Complete system back-end components
  • Implement front-end
    • Scripting of operations
    • GUI
  • Benchmark suite
biscotti conclusions
Biscotti Conclusions
  • Allows implementation of asynchronous designs
    • Without relying on commercial tools
    • Tools suited to asynchronous designs
  • Easy expansion
    • Allows rapid evaluation of researched techniques
      • Fairly compare to existing methods
    • Useful analysis techniques
  • Still incomplete