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Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

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  1. Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [LDPC for TFI-OFDM PHY] Date Submitted: [September 2003] Source: [Yaron Rashi, Eran Sharon, Prof. Simon Litsyn] Company [Infineon Technologies] Address [P.O.Box 8631, Poleg Industrial Area, Netanya 42504, Israel] Voice:[+972-9-8924100], FAX: [+972-9-8658756], E-Mail:[yaron.rashi@infineon.com] Re: [] Abstract: [comparison between LDPC and Convolution error correction codes for the TFI-OFDM PHY] Purpose: [Propose an efficient error correction layer] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15. Yaron Rashi, Infineon Technologies

  2. LDPC Efficient Alternative FEC for the TFI-OFDM PHY proposal Yaron Rashi, Infineon Technologies

  3. LDPC Introduction • Discovered by Gallager(1963), rediscovered later by Neal & Mackay (MN codes) and by Sipser & Spielman (Expander codes) • State of the art codes that exhibit Near Shannon limit performance. • Practical - Simple decoding algorithms based on Message-Passing decoding: • Low decoding complexity • allow parallel implementation – enabling high data rates • Flexibility in choice of parameters and amenability to rigorous analysis and design make it possible to design appropriate LDPC codes for many communication scenarios. • Adopted in DVB. Considered for adoption in IEEE 802.20 Yaron Rashi, Infineon Technologies

  4. n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n-k 1 1 1 1 1 1 LDPC Introduction (cont.) • A regular (dv,dc)-LDPC code is a linear block code represented by a sparse parity-check matrix H, such that each column of H contains a small fixed number dv of 1’s and each raw of H contains a small fixed number dc of 1’s. Parity-Check Matrix H Yaron Rashi, Infineon Technologies

  5. n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n-k 1 1 1 1 1 1 n-k n Variable Nodes dv=3 Parity Check Nodes dc=6 LDPC Introduction (cont.) • The code can also be represented by a bipartite graph such that the left side nodes (variable nodes) represent the codeword bits and the right side nodes (check nodes) represent the parity-check constraints on the codeword bits. dv and dc are the variable and check nodes degree of the regular code. Yaron Rashi, Infineon Technologies

  6. LDPC Introduction (cont.) • Regular LDPC codes can be generalized to irregular LDPC codes exhibiting better performance. An irregular LDPC code is represented by an irregular bipartite graph, where the degree of each left and right nodes can be different. The ensemble of irregular LDPC codes is defined by the left and right degree distributions. Yaron Rashi, Infineon Technologies

  7. Simulated System Parameters • 2 modes were simulated: Yaron Rashi, Infineon Technologies

  8. Simulated System Parameters • 3 – band simulation: Yaron Rashi, Infineon Technologies

  9. Simulation Link Budget Simulation was done according to the following link budget: Where Yaron Rashi, Infineon Technologies

  10. 122.2Mbps System Simulation • Convolution code: • Rate 1/3 64-state convolutional code G = [117, 155, 127]8 • Coded bits interleaved across tones and bands: Interleaving is done across 3 OFDM symbols, each CC output stream is interleaved and mapped to a different band. b0,0 b0,1, … b0,199 b0,0 b0,10, … b0,190 b0,1 b0,11…b0,191… b0,0 b1,0,b2,0… b0,199 b1,199 b2,199 b1,0 b1,1, … b1,199 b1,0 b1,10, … b1,190 b1,1 b1,11…b1,191… b2,0 b2,1, … b2,199 b2,0 b2,10, … b2,190 b2,1 b2,11…b2,191… Yaron Rashi, Infineon Technologies

  11. 122.2Mbps System Simulation • LDPC code: • Rate 1/3 LDPC codes with various block length where simulated • Code parameters • Left degrees: minimal degree 3, maximal degree 12, average degree 4.18 • Right degrees: minimal degree 6, maximal degree 7, average degree 6.27 • Code length: • N = 1200 bit (6 OFDM symbols), K = 400 bit (50Byte) • N = 6000 bit (30 OFDM symbols), K = 2000 bit (250Byte) • N = 24000 bit (120 OFDM symbols), K = 8000 bit (1000Byte) Yaron Rashi, Infineon Technologies

  12. 122.2Mbps System Simulation AWGN channel simulation: • 1000 packets for each distance • Packet length: 1000 Byte Capacity = -0.442dB Capacity = 31.895m Yaron Rashi, Infineon Technologies

  13. 122.2Mbps System Simulation UWB channel CM3 simulation (shadowing eliminated) • Cycled through all 100 channel realizations, 100 packets are transmitted over each channel realization. • Packet length 1000 Byte • PER is averaged over 90 best channel realizations Yaron Rashi, Infineon Technologies

  14. 480Mbps System Simulation • Convolution code: • Rate ¾ convolution code derived by puncturing of a rate 1/3 64-state convolution code G = [117, 155, 127]8 as described in TI PHY layer proposal for IEEE P802.15 task group 3a (IEEE P802.15-03/142r1) • Coded bits interleaved across tones and bands. Interleaving is done across 3 OFDM symbols (details omitted). Yaron Rashi, Infineon Technologies

  15. 480Mbps System Simulation • LDPC code: • Rate 3/4 LDPC codes with various block length where simulated • Code parameters • Code 1: N = 1200 bit (6 OFDM symbols), K = 900 bit (112.5Byte) regular (3,12)-LDPC code • Code 2: N = 3600 bit (18 OFDM symbols), K = 2700 bit (337.5Byte) irregular LDPC code: left degrees: min 3, max 8, average 3.55 right degrees: min 14 , max 15 , average 14.2 • Code 3: N = 10800 bit (54 OFDM symbols), K = 8100 bit (1012.5Byte) irregular LDPC code: left degrees: min 3, max 12, average 4 ; right degree 16 Yaron Rashi, Infineon Technologies

  16. 480Mbps System Simulation AWGN channel simulation: • 1000 packets for each distance • Packet length: 1012.5 Byte Capacity = 12.45m Capacity = 1.788dB Yaron Rashi, Infineon Technologies

  17. Complexity • Convolution code: • Studies showed that the Viterbi core for 480 mbps is feasible in75-100k gates at clock speeds ~132MHz (does that include interleaving) • LDPC code: • The same decoder architecture can be used for decoding different rate codes. Each additional code will require an additional ROM for holding the code description. • Implementation of a LDPC decoder for the 480Mbps system will require (Assuming 150Mhz clock) • Encoder complexity is approximately 25% of the decoder complexity Yaron Rashi, Infineon Technologies

  18. To Do • Redesign of the parity check matrix (H) in order to achieve improved robustness to fading and collisions. • Choose the preferred block size (code length) according to complexity-performance trade off. Yaron Rashi, Infineon Technologies