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RD50 participation in HV-CMOS submissions

This workshop discusses ongoing submissions for large monolithic sensors in HV-CMOS processes, with the aim of investigating the radiation hardness of silicon for various resistivities. The workshop also includes examples of structures for testing bulk and surface properties of HV-CMOS sensors.

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RD50 participation in HV-CMOS submissions

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  1. RD50 participation in HV-CMOS submissions G. Casse University of Liverpool V. Fadeyev Santa Cruz Institute for Particle Physics Santa Cruz, USA HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

  2. Purpose There are on-going submissions to make large monolithic sensors in HV-CMOS processes, e.g. by ATLAS pixel and strip projects. Some of the submissions are being done as Engineering Runs, which allows to use non-standard wafer resistivity, e.g. 4 values between ~20 Wcm and ~2 kWcm. RD50 could start participating in such submissions by adding dedicated structures to investigate radiation hardness of silicon for these resistivities. HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

  3. On-going Submissions There was an intention to participate in a run this spring with CHESS-2 (ATLAS strips). Interested groups: CERN, Ljubljana, Liverpool, Oxford, Santa Cruz, Glasgow, IFAE Barcelona… The run structure (reticle composition) evolved. The submission is now planned for July. Will include some test structures (next slides). The current intention is to use 1 cm2 area in September runfor dedicated RD50 investigations. => Please voice your interest and propose structures! HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

  4. CHESS-2 Examples: Bulk properties A variation of structures used in CHESS-1 submission, which are relevant for high-r substrates: Passive pixel array near edge  for Laser-TCT studies (presentations from Ljubljana) Large passive pixel array  for CCE studies with a source(presentations from Ljubljana) (possibly) “pad device”  CV meas. The main goal for including these structures is to investigate the bulk properties in a new resistivity range: depletion & CCE vs fluence. Our usual high-r (~ 3-6 kWcm) has been studied well. First studies of low-r (~ 20 Wcm) have been obtained. Non-trivial phenomena have been seen. More measurements to follow.  Now we get to investigate 3 intermediate resistivitiesto choose the best (least variation or highest minimal CCE vs fluence) HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

  5. CHESS-2 Examples: Surface properties With guard ring NO guard ring 130-150 V for 50% ff. Pixel structures with and without “guard rings”  inter-pixel isolation Similar investigation of V(bd): Typically rises with fluence. But seems to be stable with top-side biasing due to voltage drop along finite/small distances. Transistors, R, C. Electronics (0.35 mm): latch-up structures, amplifiers, etc. With guard ring NO guard ring 180 V for 30% ff. Data from I. Mandic(neutrons).  Same V(bd) at 5e15 neq/cm2 HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

  6. RD50 structures The September run: Have 1 cm2 area to use Multiple resistivities Would like to implement strip sensors: In-situ amplification to be able to study the low signal levels present in case of low r values. Omission of metal at the end of strips to enable laser scans.  Studies of CCE, depletion, R(inter-strip)  Field distribution with top and back biasing Please indicate your interest and propose your structures. HV-CMOS & RD50, 26th Workshop in Santander, Spain, June 2015

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