SEU Hardening Techniques for Retargetable, Scalable, Sub-Micron Digital Circuits and Libraries*

1. SEU Hardening Techniques for Retargetable, Scalable, Sub-Micron Digital Circuits and Libraries* M. P. Baze, J. C. Killens, R. A. Paup, W. P. Snapp Boeing Space and Communications Seattle, WA * Work supported by DTRA contract DTRA01-00-C-0046

2. “Multi-Fab” IC Design Environment • Multi-Fab environments may be – • Manufacturing design house possessing several processes • – usually with some process similarity • “Fabless” design house with access to several processes via • Single manufacturer with several processes • Third party interface, i.e. MOSIS • Independent agreements with several manufacturers

3. “Multi-Fab” Issues • Advantage of Multi-Fab Environment • Utilization of different fabrication processes as design options • Accomplished by • “Retargeting” designs to different process technologies. • or • “Scaling” designs to smaller rules in same technology. • Retargetability – Ease of design transfer to different process. • Bulk, EPI, N-Well, P- Well, Twin Tub, SIMOX, SOS, SOI-MESA, Twin Tub, Single Poly, Dual Poly, # Metal Layers, Resistor Types, Capacitor Types, Device Models, etc. • Scalability – Ease with which a design can be scaled down in • feature size, without sacrificing the advantages of scaling.

4. Retargeting and Scaling Designs VHDL Design C (BC30) VHDL Design A (8051) VHDL Design B (1773) Standard Digital Cell Functions Library A Process A Library B Process B Library B/2 Process B/2 Targeting / Scaling Synthesis

5. Retargeting and Scaling Designs SEU Hardening cap.s, filters, redundant, Idrive, etc. VHDL(H1, H3) Design C (BC30) VHDL (H1, 2, 3) Design A (8051) VHDL (H2, H3) Design B (1773) HARD 2 HARD 3 HARD 1 A-3 A-1 Process A A-2 B-1 B-2 Process B B/2-3 B/2-2 Process B/2 Synthesis Targeting / Scaling

6. Basic SEU Hardening Options • Three Categories of SEU Hardening Techniques • 1. Charge Dissipation - Consumes power • 2. Temporal Filtering - Reduces speed • 3. Spatial Redundancy - Consumes area • Charge Dissipation & Temporal Filtering - Increase LETT • Spatial Redundancy – Reduce effective X-section

7. Charge Dissipation Increase Transistor Current Drive “STANDARD” NAND2 VDD OUT Sink QCOL to prevent “valid” pulse widths where “valid” > register TSH IN0 IN1 VSS VDD transistor IDRIVE > QCOL / Register TSH HARDENED NAND2 OUT IN0 • Scalability • Speed – no significant penalty • Area – in proportion to drive • Power – in proportion to drive • Retargetability • Increases area of standard cell library IN1 VSS

8. Charge Dissipation Adding Capacitors in Combinational Logic VDD + + 1) Keep direct hit from crossing ½ VDD - Required Cap > 2 x (QCOL / VDD) IN0 OUT IN1 2) Keep input transient from crossing ½ VDD Required Cap > 2 x IDRIVE x PW / VDD : however since PW ~ QCOL / IDRIVE “upstream” , then - Required Cap > 2 x (QCOL / VDD), independent of global IDRIVE sizing Capacitor Set Hardness Cap> 2 x (QCOL / VDD) Trade power vs speed with global transistor sizing • Retargetability • Implemented by adding/sizing cap’s to standard soft library • Scalability • Speed, power, area penalties may negate many advantages of scaling

9. Charge Dissipation / Temporal Filtering Adding Capacitors in sequential logic + + 1) Keep direct hit from crossing ½ VDD - Required Cap > 2 x (QCOL / VDD) 2) Lengthen TSH - short input transients “invalid” Register TSH > QCOL / transistor IDRIVE Capacitor • Retargetability • Implemented by adding/sizing cap’s to standard soft library • Scalability • Speed, power penalties may negate many advantages of scaling

10. Temporal Filtering “Delay-and-Vote” Combinational logic Network Voting Circuit out in delay delay delay Total Delay = 2 x Error Pulse Width ~ 2 x (QCOL / IDRIVE ) if IDRIVE = 0.25 mA and QCOL = 0.4 pC then 2 x (QCOL / IDRIVE ) = 3.2 ns • Retargetability • Architecture implementation. Delay element redesign for each process. • Scalability • If QCOL does not scale down with IDRIVE, the required delay increases

11. Spatial Redundancy - TMR Triple Mode Redundancy (TMR) Error on OUT requires simultaneous errors in 2 or more logic networks Logic Network OUT INPUTS • Doesnot increase LET threshold • Does reduce effective cross-section by • geometric probability of multiple node hit Voting Circuit Logic Network Logic Network X-sec EFF ~ 1 / (node separation)2 ~3X power and area penalty • Retargetability • Architecture implementation. • Modified structural netlists and/or cells • Scalability • Adequate separation is critical

12. TMR - Node Separation Triple Redundant Flip/flops Vdd D Q CLR Bad Layout Practice - “Rail stacking” of voted F/F’s Adjacent redundant elements 1 CLK PRE Q 2 voter Vdd D Q CLR 3 CLK PRE

13. D D D Q Q Q CLR CLR CLR CLK CLK CLK PRE PRE PRE TMR - Node Separation Triple Redundant Flip/flops Vdd Q voter 1 2 3 • Acceptable Layout • - “Sequencing” of voted F/F’s • Places redundant elements at greater distance

14. Internally Redundant Logic Places redundant nodes in very close proximity - Cell layout critical Vdd Isolated Well Transistors* “Dual Data Stream” redundant logic** Vdd PA PB PA PB Pdrive PC PC Pshunt Pout P isolation Pout Vdd OUT Vdd IN Nout Nout Nshunt N isolation NA NA NB Ndrive NC NC NB • Retargetability • Non-standard library cells. • Transistors often need sizing to maintain performance. • Scalability • Adequate separation is critical *Baze, et, al. IEEE NSREC ’00, pg 2609 **Wiseman, IEEE Rad. Data Workshop, ’94, pg51

15. Redundant state nodes PMOS PMOS BASIC LATCH PMOS PMOS Internally Redundant Latch Cross Coupled (asymmetric) • Retargetability / Scalability • Requires custom sizing of six transistors with each new process to balance the single node SEU response and achieve adequate hardness

16. clock data Internally Redundant Latch DICE* - Dual interlocked storage cell Less sensitive to transistor sizing ** Table 2. Single Event Effects Test Results ** *Calin, et al, IEEE NSREC ’96, pg2877 **Alexander, et al. GOMAC 2001 Digest ofPapers, pg 257

17. CLKB1 CLK Q CLKB2 CLK CLKB1 CLKB2 CLK CLK Low Power DICE Latch with PRE / CLR CLK PRE • Low Power – pass gates • Clear • Preset • Output buffer CLKB2 D CLK CLR CLKB1

18. CLKB1 CLK Q CLKB2 CLK CLKB1 CLKB2 CLK CLK DICE Latch Layout Restrictions CLK PRE No two same color transistor blocks may be paced side by side CLKB2 D CLK CLR CLKB1

19. PRE CLKB2 CLK CLK CLKB1 CLKB2 CLK CLK CLKB1 D CLKB2 CLK Q CLKB2 CLK CLK CLKB1 CLK CLK CLKB2 CLR CLK CLKB1 CLKB1 DICE Flip/Flop • Retargetability • Transistor sizing and pass gate/ logic implementations may need to be traded to optimize speed vs. power • Scalability • Single node hardness insensitive to transistor sizing. Node separation is critical

20. Flip/Flop Comparisons • Retargetable / Scalable Flip/Flops in a Single Process HARDNESS* (e/b-d) POWER (CLK-Q) SPEED (TSH) AREA (mm2) Rise – 0.7 mW Fall – 0.2 mW 10-8 1 node Rise – 0.21 ns Fall – 0.27 ns Std Low Power 360 2x10-9 1 node Rise – 1.0 mW Fall – 0.2 mW Increased IDRIVE Rise – 0.16 ns Fall – 0.15 ns 460 Low Power triplicate-and-vote Rise – 1.72 mW Fall – 1.27 mW Rise – 0.21 ns Fall – 0.27 ns 10-11 2 node 1200 Rise – 1.4 mW Fall – 1.1 mW DICE Rise – 0.96 ns Fall – 0.97 ns 1.6 x10-10 2 node 520 *preliminary estimates for a proposed SOI process, GEO orbit

21. Summary A number of design options exist for improving the SEU hardness of digital logic. However, specific considerations and restrictions must be observed for each technique if these techniques are to be applied over a range of process technologies and reduced feature size.