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DDR333 – The New Wave

DDR333 – The New Wave. Bill Gervasi Technology Analyst, Transmeta Corporation Chairman, JEDEC Memory Parametrics. RAM Evolution. 3200MB/s. Mainstream Memories. DDR400. 2700MB/s. DDR333. 2100MB/s. “DDR II”. DDR266. 1600MB/s. DDR200. Simple, incremental steps. 1100MB/s. “DDR I”.

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DDR333 – The New Wave

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  1. DDR333 – The New Wave Bill Gervasi Technology Analyst, Transmeta Corporation Chairman, JEDEC Memory Parametrics

  2. RAM Evolution 3200MB/s MainstreamMemories DDR400 2700MB/s DDR333 2100MB/s “DDR II” DDR266 1600MB/s DDR200 Simple,incrementalsteps 1100MB/s “DDR I” PC133 “SDR”

  3. Key to System Evolution • Never over-design! • Implement just enough new features to achieve incremental improvements • Use low cost high volume infrastructure • Processes • Packages • Printed circuit boards

  4. New DDR Specifications • DDR Components & Modules • DDR333 chips • PC2700 MicroDIMM • PC2700 SO-DIMM • PC2700 Registered DIMM • PC2700 Unbuffered DIMM • DDR Component Packaging • 66 pin TSOP-II • 60 ball FBGA

  5. DDR333 • 333 MHz data rate per pin • Approved for both TSOP and FBGA • First introduction of FBGA into SDRAM family • One package-dependent timing consideration • Most improvements from tighter DLL design • Purpose of the DLL is accurate delivery of data and strobes during read cycles

  6. Achieving 333 MbpsData Rate

  7. DLL Effects CK • Clock jitter, pulse width distortion, DQS pull in or push out from pattern effects, p-channel to n-channel variation CK DDR266 = 750 psDDR333 = 600 ps tDQSCK* DQS

  8. Data Capture Parameters • Data pin skew, simultaneous switching output effects, output driver variation • Note that data valid window width is package independent! DQS tDQSQ* tQHS* (simplified view) data DDR266 = 750 psDDR333 = 550 ps for TSOP = 500 ps for FBGA DDR266 = 750 psDDR333 = 450 ps for TSOP = 400 ps for FBGA

  9. Managing Power

  10. Power = CV2f% Factors: • Capacitance (C) • Voltage (V) • Frequency (f) • Duty cycle (%) • Power states Keys to lowpower design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

  11. 2.5V Signaling = Power Savings 2.5V VDDQ 1.60V DDR3332.5X@ 2.5V VIHac 1.43V VIHdc 1.25V VREF VILdc 1.07V PC1331X@ 3.3V VILac 0.90V VSS

  12. Package Capacitance (pF) TSOP-II Package Min Max Delta • Reduced capacitance lowers power, makes design easier Input Capacitance 2.0 3.0 0.25 Input/Output Capacitance 4.0 5.0 0.50 Approximate 10-25% reduction FBGA Package Input Capacitance 1.5 2.5 0.25 Input/Output Capacitance 3.5 4.5 0.50

  13. Serves Many Market Segments • Servers, Workstations: • High bandwidth, high capacity • Registered DIMMs • Desktop PCs, Network Routers: • Low latency • Unbuffered DIMMs and SO-DIMMs • Mobile, Handheld: • Low power • SO-DIMMs and MicroDIMMs

  14. Wide Spread Support • DRAM suppliers • Infineon, Micron, Mitsubishi, Nanya, Samsung, and others • Modules suppliers • ATP, Kentron, Kingston, Melco, Micron, PNY, Samsung, and others • Users • ALi, AMD, Intel, SiS, Via, Transmeta, and others Rapid adoption throughout the industry has begun

  15. DDR 333 • Memory of choice for the future • Simple transition from DDR266 • Widespread adoption in all market segments

  16. Thank You

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