1 / 21

ECE122 – 30 Lab 3: VTC & Layout

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 – 30 Lab 3: VTC & Layout. Jason Woytowich September 16, 2005. 5V. Vout. 0V. 0V. 5V. Vin. Voltage Transfer Characteristic.

ktreadway
Download Presentation

ECE122 – 30 Lab 3: VTC & Layout

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 – 30 Lab 3: VTC & Layout Jason Woytowich September 16, 2005

  2. 5V Vout 0V 0V 5V Vin Voltage Transfer Characteristic • Vin on the X-Axis and Vout on the Y-Axis

  3. Voltage Transfer Characteristic • A symmetric VTC is one where the Vin vs Vout curve crosses through the dead center of the graph. • Using 5V inputs and outputs this point is 2.5V in and 2.5V out

  4. Lab activity • Find Wp/Wn such that the VTC for an inverter is symmetric.

  5. Layout Using L-Edit • Create a module of a buffer, using SCMOS inverters • Don’t forget to make a symbol for it

  6. Layout Using L-Edit • Instance your buffer into a new module and add pads to the inputs and outputs. • I called it Buffer_wPads

  7. Layout Using L-Edit • Export your design as a tpr file.

  8. Layout Using L-Edit • Open L-Edit • Replace Setup: C:\TannerLib\SCMOS\mhp_n05d.tpr

  9. Layout Using L-Edit • Go to SPR->Setup • Fill in the paths for the tech library and your netlist

  10. Layout Using L-Edit • Go to SPR->Place and Route, Hit Run

  11. Layout Using L-Edit • If it completes correctly you will see this:

  12. Layout Using L-Edit

  13. Layout Using L-Edit

  14. Layout Using L-Edit • Cross sections • Process Definition File is C:\Program Files\Tanner EDA\L-Edit 11.0\samples\tech\mosis\mhp_n05.xst

  15. Layout Using L-Edit

  16. Simulating Your Layout • Once the we have a layout we can simulate our design with parasitic capacitances. • First draw ports over each of the pad with Metal3 selected. • Give them descriptive names

  17. Simulating Your Layout • Copy the file C:\TannerLib\tech\mosis\mhp_n05.ext into your working directory • Make the following modification # Linear capacitor using Cap-Well # device = CAP( # RLAYER=cap using Cap-Well; # Plus=poly wire; # Minus=ndiff; # MODEL=; # )

  18. Simulating Your Layout • Go to Tools->Extract

  19. Simulating Your Layout

  20. Simulating Your Layout • Open the output in T-Spice • Add simulation commands and power supplies • Replace signal names where necessary .include "C:\Program Files\Tanner EDA\T-Spice 9.1\models\ml2_125.md" .tran/powerup 2n 400n method=bdf .print tran v(Pad_Input,Ext_Gnd) v(Pad_Output,Ext_Gnd) V1 Ext_Vdd Ext_Gnd 5.0 V2 Pad_Input Ext_Gnd PULSE (5V 0V 0 1n 1n 50n 100n)

  21. Homework • Implement the following functions as a single module using only NAND gates from the SCMOS library. • Test and layout. • Extra points for optimal designs X = ((!A)B + A(!B)C) Y = (B(!C) + A(!B)C)

More Related