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C H A P T E R

C H A P T E R. 3. ARM 汇编语言编程. ARM 汇编基础. ★ The following is a simple example which illustrates some of the core constituents of an ARM assembler module:. Label. opcode. operands. comment. General Layout of an Assembly Program. The general form of lines in an assembler module is:

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C H A P T E R

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  1. C H A P T E R 3 ARM汇编语言编程

  2. ARM汇编基础 ★The following is a simple example which illustrates some of the core constituents of an ARM assembler module: Label opcode operands comment

  3. General Layout of an Assembly Program • The general form of lines in an assembler module is: label <space> opcode <space> operands <space> ; comment • Each field must be separated by one or more <whitespace> (such as a space or a tab). • Actual instructions never start in the first column, since they must be preceded by whitespace, even if there is no label. • All three sections are optional and the assembler will also accept blank lines to improve the clarity of the code.

  4. Description of Module • The main routine of the program (labelled start) loads the values 15 and 20 into registers 0 and 1. • The program then calls the subroutine firstfuncby using a branch with link instruction (BL). • The subroutine adds together the two parameters it has received and places the result back into r0. • It then returns by simply restoring the program counter to the address which was stored in the link register (r14) on entry. • Upon return from the subroutine, the main program simply terminates using software interrupt (SWI) 11. This instructs the program to exit cleanly and return control to the debugger.

  5. AREA, ENTRY & END Assembly Directives • Directives are instructions to the assembler program, NOT to the microprocessor • AREA Directive - specifies chunks of data or code that are manipulated by the linker. • A complete application will consist of one or more areas. The example above consists of a single area which contains code and is marked as being read-only. A single CODE area is the minimum required to produce an application. • ENTRY Directive - marks the first instruction to be executed within an application • An application can contain only a single entry point and so in a multisource-module application, only a single module will contain an ENTRY directive. • END directive - marks the end of the module

  6. Creating program and project file • Invoke ARM_SDK program and enter the program as example1.s in the directory H:\arm_work\eg1\ • Use pulldown command >Project >New to create a new project called example1.apj • Add all the files belonging to this project as shown (only one file here):

  7. How to interpret the Project File (.apj)?

  8. Build and Run the program • After building the project, you can invoke the debugger program and step through each instructions one at a time. • The debugger program allows you to control the execution while viewing any register and memory location. • You can also set breakpoints in the program.

  9. 数据处理指令(Data Processing Instructions) • Three types of instructions: • Data Processing • Data Movement • Control Flow • Rules apply to ARM data processing instructions: • All operands are 32 bits, come either from registers or are specified as constants (called literals) in the instruction itself • The result is also 32 bits and is placed in a register • 3 operands - 2 for inputs and 1 for result • Example: ADD r0, r1, r2 ; r0 := r1 + r2 • Works for both unsigned and 2's complement signed • This may produce carry out signal and overflow bits, but ignored by default • Result register can be the same as an input operand register

  10. Data Processing Instructions – Arithmetic operations • Here are ARM's arithmetic operations: • ADD r0, r1, r2 ; r0 := r1 + r2 • ADC r0, r1, r2 ; r0 := r1 + r2 + C • SUB r0, r1, r2 ; r0 := r1 - r2 • SBC r0, r1, r2 ; r0 := r1 - r2 + C - 1 • RSB r0, r1, r2 ; r0 := r2 - r1 • RSC r0, r1, r2 ; r0 := r2 - r1 + C - 1 • RSB stands for reverse subtraction • Operands may be unsigned or 2's complement signed integers • 'C' is the carry (C) bit in the CPSR - Current Program Status Reg • ADC, SBC, and RSC are used to operate on data more than 32 bits long in 32-bit chunks

  11. ADC, SBC, RSC • For example, let’s add two 64-bit numbers X and Y, storing the • result in Z • We need two registers per number • store X is r1:r0, Y in r3:r2, and Z in r5:r4 (notation – MSW:LSW) • Then: • ADDS r4, r0, r2 • ADC r5, r1, r3 • “S” at the end of an instruction means you want to keep a record of the status of this operation in the C, V, N, and Z flags in the CPSR (lots more on this later) • Similarly, if we wanted to subtract the two numbers: • SUBS r4, r0, r2 • SBC r5, r1, r3

  12. ADC, SBC, RSC • Some of you are probably thinking “why + C – 1”?! • Remember that subtraction is performed by using two’s complement addition – for X-Y: • find the two’s complement of Y • add this value to X • Finding the two’s complement involves inverting all bits, adding 1 • You only want to add one to the least significant bit in the least significant word • So for all following words, this “added 1” needs to be subtracted off • In practice, you will rarely want to use arithmetic on more than 32-bits

  13. Data Processing Instructions – Logical operations • Here are ARM's bit-wise logical operations: • AND r0, r1, r2 ; r0 := r1 and r2 (bit-by-bit for 32 bits) • ORR r0, r1, r2 ; r0 := r1 or r2 • EOR r0, r1, r2 ; r0 := r1 xor r2 • BIC r0, r1, r2 ; r0 := r1 and not r2 • BIC stands for 'bit clear', where every '1' in the second operand clears the corresponding bit in the first

  14. Data Processing Instructions - Register Moves • Here are ARM's register move operations: • MOV r0, r2 ; r0 := r2 • MVN r0, r2 ; r0 := not r2 • MVN stands for 'move negated'

  15. Data Processing Instructions – Comparison Operations

  16. Data Transfer Instructions - single registerload/store instructions

  17. Data Transfer Instructions - Set up the address pointer

  18. Data Transfer Instructions - ADR instruction

  19. Data Transfer Instructions - Base plus offsetaddressing • Extend the copy program further to copy NEXT word:

  20. Data Transfer Instructions - pre-indexed withauto-indexing

  21. Data Transfer Instructions - post-indexedaddressing

  22. Data Transfer Instructions Summary

  23. More on assembly languageprogramming

  24. The S-bit

  25. Conditional Branch Instructions

  26. BCC-BLO, BCS-BHS equivalence

  27. Conditional Execution

  28. Conditional Execution - more

  29. Conditional Execution - Summary

  30. The more complex cases

  31. Shifted Register Operands

  32. ARM shift operations - LSL and LSR

  33. ARM shift operations - ASL and ASR

  34. ARM shift operations - ROR and RRX

  35. A simple assembly language program- Hello world!

  36. Another Example: Block copy • Here is another example to block copy from one address (TABLE1) to another (TABLE2), then write it out:

  37. Stacks and Subroutines

  38. Load/Store Multiple Instructions

  39. Update base address register with Load/Store Multiple Instructions

  40. Example of using Load/Store Multiple

  41. The four variations of the STM instruction

  42. The idea of a STACK

  43. PUSHing onto a Stack

  44. Stack view of STM instructions

  45. POP operation

  46. The four different ways of implementing a stack

  47. Relationship between the two different views of LDM/STM instructions

  48. Subroutines

  49. Subroutine (con't)

  50. Nested Subroutines

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