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CSE 140 Lecture 15 System Designs

CSE 140 Lecture 15 System Designs. Professor CK Cheng CSE Dept. UC San Diego. System Designs. Introduction Components Spec Implementation. Digital Designs vs Computer Architectures. Instruction Set (H.Chapter 6, CSE141) Bottleneck: Silicon Area, Power Data Path (H.Chapter 7.1-7.3)

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CSE 140 Lecture 15 System Designs

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  1. CSE 140 Lecture 15System Designs Professor CK Cheng CSE Dept. UC San Diego

  2. System Designs • Introduction • Components • Spec • Implementation

  3. Digital Designs vs Computer Architectures • Instruction Set (H.Chapter 6, CSE141) • Bottleneck: Silicon Area, Power • Data Path (H.Chapter 7.1-7.3) • Control Subsystem (H.Chapter 7.1-7.3) • Memory Management (Chapter 8, CSE141) • Bottleneck: IO, Memory Latency

  4. Introduction • Methodology • Approach with success stories • Hierarchical designs with interface between the levels • Data Subsystem and Control Subsystem • For n-bit data, each operation takes n or more in complexity • Data subsystem carries out the data operations and transports • Control system sequences the data subsystem and itself.

  5. I. Introduction 64 Data Subsystem 64 Data Inputs Data Outputs Control Signals Conditions Control Subsystem Control Outputs Control Inputs go done (ready)

  6. Introduction Functions Data storage Data operations Data transport Control of data operations Control of data transports Control of the sequential system Components Storage Modules Operators Interconnections Sequential machines Data Subsystem Control Subsystem

  7. Data Subsystem Components • Storage • Operator • Interconnect

  8. Components: Storage Modules, Register D CLK LD CLR Q Q(t+1) = (0, 0, .. , 0) if CLR = 1 = D if LD = 1 and CLR = 0 = Q(t) if LD = 0 and CLR = 0

  9. Storage Component: Registers, Array of Registers D LD C Registers: If C then R  D R Array of Registers: Sharing connections and controls D Decoder address LD C R

  10. Storage Components: RAM, FIFO, LIFO RAM RAM Decoder Address Size of RAM larger than registers Performance is slower FIFO (First in first out) LIFO (Stack)

  11. Functional Modules B A CASE Op-Sel Is When F1, Z <= A op1 B When F2, Z <= A op2 B . . End CASE Operation selection Z

  12. Interconnect Modules (Wires and Switches) • Single Lines • Band of Wires • Shared Buses • Crossbar 1. Single line (shifting, time sharing)

  13. 2. Band of Wires (BUS) 3. Shared Bus switch switch switch switch ….. R1 R2 R3 Rm Switches x x DEMUX MUX c c d 1 2 3 .. N 1 2 3 .. N y y

  14. 4. Crossbar (Multiple buses running horizontally) m simultaneous transfers are possible, but more expensive. 64 Bus 1 R1 Bus m Rm MUX MUX MUX …

  15. Program: • Objects (Registers, Outputs of combinational logic) • Operation • Assignment • Sequencing Example: Signal R1, R2, Bit Vector V[15:0]; Z  A + B ( A, B, Z need to be defined) R1  R2 Begin End if ( ) then ( ), ENDIF;

  16. S1 Ex. If C then R1 S1 Else R2  S2 Endif; R1 LD S2 C R2 If C1 then X  A Else X  B + C Endif If C2 then G  X Endif A B C Adder 1 0 MUX C1 G C2 CLK

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