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Low-Cost CLT-Based Random Number Generator for Communication Test

Low-Cost CLT-Based Random Number Generator for Communication Test. Presenter: Pin-Chong Chen Advisor: Tsung-Che Huang. 2009/11/30. References.

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Low-Cost CLT-Based Random Number Generator for Communication Test

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  1. Low-Cost CLT-Based Random Number Generator for Communication Test Presenter: Pin-Chong Chen Advisor: Tsung-Che Huang 2009/11/30 SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  2. References Y.-H. Chou, T.-H. Wu and T.-C. Huang, “Low-Cost CLT-based Random Number Generator for Communication Test,”VLSI Test Technology Workshop (VTTW), Test Applications, pp.79-82, Taiwan, Jul. 2009. SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  3. Outline • Introduction • Previous Work • Random Number Generator (RNG) • Normal Distribution RNG • Uniform Distribution RNG • Programmable Delay Line (PDL) • Coarse-tuned PDL • Fine-tuned PDL • Experiment Results • Conclusions SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  4. Introduction • In high-speed computer and communication systems, timing jitter is one of the most critical parameters. • Jitter testing is becoming indispensable. • Conventional Jitter Generator is executed by expensive external testers or instruments. • This paper develop a CLT-based Random Number Generator for Communication test. SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  5. Ideal and Jitter Waveform Waveform transition is too early Ideal Waveform Waveform transition is too late • Jitter is defined as the short-term variations of a digital signal’s significant instants from their ideal positions in time. Fig. 1 Jitter Waveforms SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  6. RNG (Screening Sampling) • Box-Muller (1) • Ziggurat Algorithm Fig. 2 Typical Ziggurat Algorithm SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  7. RNG (Direct Sampling) • Table LookUp Fig. 3 Typical Table LookUp Methods SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  8. Conventional CLT-based RNG • The conventional CLT approves the sum of m independent random variables with uniform distribution, it will be approaching to a normal distribution. Fig. 4 A Conventional CLT-based RNG SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  9. Proposed CLT-based RNG Where k is a non-negative integer Fig. 5 Proposed CLT-based RNG SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  10. LFSR-based Uniform Distribution RNG/JG Fig. 6 Uniform Distribution RNG Fig. 7 Uniform Distribution Jitter Generator SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  11. CPDL Fig. 8 Coarse-tuned Programmable Delay Line • The jitter distribution control block can include several XOR gates for a uniform distribution RNG or be normal distribution RNG. SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  12. FPDL Fig. 9 Fine-tuned Programmable Delay Line SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  13. Proposed CLT Layout The proposed CLT RNG sourced from 12 type-I 16-bit LFSR. TSMC 0.13um CMOS 1P8M Table 1 Area Comparisons 47% area reduce Fig. 10 Layout of a CLT-based RNG SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  14. Randomness: Scatter Diagram Fig. 11 Scatter diagrams with 10,000 entries of 16-bit outputs SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  15. Goodness of Fit • In Communication test, the fitness is more critical than the randomness. (2) Fig. 12 Fitting Sampled Number to a Normal Distribution SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  16. Experiment Results Table 2 Comparison of Proposed Conventional CLT-based RNGs SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  17. Conclusions • In this paper we proposed a theorem to reduce the parallel counter in conventional type-I LFSR-sourced CLT-based RNG to a parallel 1’s counter. • More than 93% of counterarea can be saved mainly due to the reduced register length for a16-bit fraction system. • About 47% of area and 30% of adder levels, namely the propagation time can be reduced. • We proposed a jitter generator embedded in network on-a-chip or system-in-a-package for communication test. SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

  18. Thanks for your attention. SoC Design Lab, Electronic Engineering, National Changhua University of Education, Taiwan, R.O.C

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