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Paper Report. A h ybrid approach to the test of cache memory controllers embedded in SoCs ’. W. J. Perez, J. Velasco Universidad del Valle Grupo de Bionanoelectronica Cali, Colombia D. Ravotto , E. Sanchez, M. Sonza Reorda Dipartimento di Automatica e Informatica Torino, Italy

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paper report

Paper Report

A hybrid approach to the test of cache memory controllers embedded in SoCs’

W. J. Perez, J. Velasco

Universidad del Valle Grupo de Bionanoelectronica Cali, Colombia

D. Ravotto, E. Sanchez, M. SonzaReorda

Dipartimento di Automatica e Informatica Torino, Italy

14th IEEE International On-Line Testing Symposium 2008

Presenter: Jyun-Yan Li

abstract
Abstract
  • Software-Based Self-Test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing a particularly complex module to test is the cache controller, due to its limited accessibility and observability.
  • In this paperwe propose a hybrid methodology that exploits an Infrastructure Intellectual Property (I-IP) to complement an SBST algorithm for testing the data and instruction cache controller of embedded processors in SoCs. In particular, the I-IP may be programmed to monitor the system buses and generate the appropriate feedback about the correct result of the executed programs (in terms of obtained hit or miss operations). The effectiveness of the proposed methodology is evaluated resorting to a sample SoC design.
what is the problem
What is the Problem
  • The testing cost is more and more high
    • How to generate effective test program in the SBST
  • Some of case in [8] the timer could not be available or usable
    • Using timer to ensure cache hit or miss event
      • Assume the hit or miss max time
related work
Related work

Test cache

Hardware based

Software based

No require special

Require special system for memory writing & reading when cache is disable

Modify cache structure to improve IDDQ testing

[3]

Direct transformation of March-like test

[5-7]

SBST strategy for data cache

[8]

Using March C- algorithm in the MBIST device

[4]

enhance

This paper

proposal method outline
Proposal method outline
  • Data cache algorithm
  • Instruction cache algorithm
  • Address calculation function
    • Marching 0: The unique bit is 0 in the tag bits
    • Marching 1: The unique bit is 1 in the tag bits
data cache flow chart
Data cache flow chart

start

Yes

Rx⊕Ry=0?

Nd*Nb times?

No

No

Calculate address (A)

Yes

error

Calculate address (A)

Write data (b) at A address

Nd*Nb times?

No

Read data (Rx,b) at A address

W miss

Yes

R miss

Read data (Rx) at A address

end

Write data (b) at A address

R hit

W hit

Yes

Rx=b?

Read data (Ry) at A address

No

R hit

error

address calculation function
Address calculation function
  • Purpose
    • access to every position of each cache block
    • Fully excite all circuits correlated with the tag, index and offset
  • Address = As + a_tag + a_index + a_offset

D$

I$

Avoid overlapping, while cache fills tag consecutively

example
Example
  • Assume As=0x00000000, Cs=8KB, Bs=16B, Ds=4B, Ms=256KB
    • Nb = 8KB/16B = 512 blocks
    • Nd = 16B/4B = 4 word
  • n=0, m=1
    • D$ Address = = 00010 000000001 0100
  • n=1, m=1
    • I$ Address = = 11101 000000001 0100

Nt: number of bits required to address the cache block (as the tag bit)

n: current data in the block

m: current block in the cache

1 mod 5=1

tag

offset

index

(1+0) mod 4=1

Marching one

Marching zero

example cont
Example (cont.)
  • The result address after calculating

n=0 m=0

n=0 m=1

n=1 m=0

n=2 m=0

n=4 m=0

instruction cache flow chart
Instruction cache flow chart

Placed in cache non-cacheablefor avoiding the loading in the cache of the respective machine code

start

Calculate address (A)

Jump to A address

R miss

Address A routine

Jump to A address

R hit

Address A routine

exception

Nd*Nb times?

No

Yes

error

end

experimental result
Experimental result
  • OpenRISC 1200
  • Result

Prevents the register to change some bit in the higher part of address without exception when memory exchange

conclusion
Conclusion
  • A mixed methodology for testing the data and instruction cache control part
  • A high stuck-at fault coverage with reduced cost
  • My comment
    • No discuss about I-IP how to connect with processor
    • The ARM10 patterns have similar algorithm for data cache verification