Dual Damascene

1. Dual Damascene IC Manufacturing

2. Technical Trends • In modern IC’s with many active elements need high levels of signal integration • This has necessitated as many as eight layers of high density interconnects • The electrical resistance and parasitic capacitance associated with these metal interconnections has become a major factor that limits the the circuit speed of such high performance IC’s • This limitation has been the fundamental motivating factor for the industry’s move away from aluminium interconnect material and silicon dioxide dielectric between the lines

3. Technical Trends • Copper lowers the resistance of the interconnect lines and increases their reliability (electromigration) • Low-k dielectrics reduce the parasitic capacitance between the lines • These new materials are employed in a process called ‘Dual Damascene’. • The initial transition to dual damascene employed employed Cu with traditional silicon dioxide – recent trend is to include the low-k dielectric

4. Motivation • The primary driver for the dual damascene approach is that copper does not form a volatile by-product - it is very difficult to etch • Copper metallisation schemes cannot be realised using the traditional subtractive etch approach • The dual damascene technique overcomes this problem by: • Etching a columnar hole, followed by a trench etch into the ILD • Filling both structures with copper • Polishing it back

5. Trench-First Approach (3) (2) (1) (4) (5) (6)

6. Trench-First Approach (1) Low-k ILD stack fabricated on copper – sandwiched between SiN Barriers with SiN ‘Stop Layer’ in middle (2) The wafers are coated with photoresist and lithographically Patterned (3) An anisotropic dry etch cuts through the surface hard-mask And down through the low-k dielectric, stopping on the stop layer

7. Trench First Approach (4) Photoresist is again applied to the wafer and lithographically patterned (5) Dry etch cuts through embedded etch stop and down through The ILD, to the final Silicon Nitride barrier located at the Bottom of the Via (6) The bottom barrier is them opened with a special etch and the Photoresist is stripped

8. Trench-First Approach (7) A thin barrier (Ta/TaN) is deposited which lines the Dual Damascene structure and acts as a barrier to prevent the copper From diffusing into the ILD (8) A copper seed layer is deposited (ALD/PVD/CVD) (9) The bulk copper is deposited (via electroplating) (10) The copper is polished back using CMP (11) A Silicon Nitride barrier is deposited on top to encapsulate The copper

9. Drawback of Trench-First • Pooling of resist in trenches creates local regions of extra-thick resist in the areas where vias have to be patterned • Forming very fine via structures in such thick resist is extremely difficult (sub 0.25µm)

10. Via-First Approach (1) (2) (3) (6) (5) (4)

11. Via First Approach (1) Low-k ILD stack fabricated on copper – sandwiched between SiN Barriers with SiN ‘Stop Layer’ in middle (2) The wafers are coated with photoresist and lithographically Patterned (3) An anisotropic etch cuts through the surface hard mask, down through the ILD and the embedded etch stop, stopping On the bottom silicon nitride barrier (it is important that the via etch does not break through the Bottom Silicon Nitride layer – if it does the process will sputter The copper located beneath the barrier up into the unprotected Via hole. The copper will diffuse quickly into the ILD – leading to Device failure)

12. Via First Approach (4) Via photoresist is stripped and trench photoresist is applied And lithographically patterned – some of the photoresist will Remain at the bottom of the via, and prevent the lower portion of The via from being over-etched during the trench etch process (5) An anisotropic etch then cuts through the surface hard mask And down through the ILD, stopping on the embedded hard Mask – this forms the trench (6) The photoresist is then stripped and the Silicon Nitride barrier At the bottom of the via is opened with a very soft, low energy Etch that will not cause the underlying Copper to sputter into the via

13. Via First Approach (7) A thin barrier (Ta/TaN) is deposited which lines the Dual Damascene structure and acts as a barrier to prevent the copper From diffusing into the ILD (8) A copper seed layer is deposited (ALD/PVD/CVD) (9) The bulk copper is deposited (via electroplating) (10) The copper is polished back using CMP (11) A Silicon Nitride barrier is deposited on top to encapsulate The copper

14. Via First Approach The via-first approach has been widely adopted for small geometry Devices It avoids the pooling associated with the trench-first approach The only pooling that occurs happens at the bottom of the already Formed via – which has the beneficial effect of shielding the lower Via from the trench etch

15. Integration Challenges • With ultra – low – k materials, significant contact between photoresist and the low-k material may result in absorption of the photoresist material into the insulator – altering the k-value • This is especially a problem for via-first approaches

16. Integration Challenges • Most low-k materials are hydrophilic. The CMP process is a wet process involving direct contact between water and the wafer surface. • The surface hard mask, located at the surface of the top of the ILD stack must • Shield the ILD from the moisture on the CMP Process • Protect the ILD from aggressive cleans • Block copper diffusion • Act as a CMP Stop

17. Integration Challenges • The point in introducing the low-k material is to lower the interlayer capacitances • The permittivity of Silicon Nitride is relatively high (6<k<8) • Including it in the low-k stack raises the overall permittivity – compromising the stack’s ability to mitigate electrical delay • Alternative materials need to be found – this is non-trivial