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Implementing a 1024-bit RSA on FPGA. Jing Lu Qian Wan. Outline. Motivation System Architecture Implementation Testing. Motivation. Network hosts and devices are threatened by virus, worms, and all sorts of attacks

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Implementing a 1024-bit RSA on FPGA


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Presentation Transcript
slide2

Outline

  • Motivation
  • System Architecture
  • Implementation
  • Testing
slide3

Motivation

  • Network hosts and devices are threatened by virus, worms, and all sorts of attacks
    • vulnerability of common software applications or lack of secure control and protection mechanisms.
  • Networking applications using reconfigurable hardware devices become popular
    • Low cost, high performance and flexibility, and immunity to worms and virus.
    • Applications include extensible network routers, firewalls, and Internet-enable sensors, etc.
slide4

Motivation

  • These devices are distributed in a large geographic area and operate over public networks
    • Robust security mechanisms for remote control and configuration are highly needed.
  • RSA algorithm is a secure, high quality, public key algorithm. It can be used in these applications as a method for exchanging secret information such as secret keys and source authentication.
slide5

Motivation

  • Design Goal
    • WORK (optimize it later)
    • High system frequency
      • Short critical path
    • Small area
      • Reuse modules
      • No pipeline
    • Low power
      • Compute only when needed
    • Reasonable high throughput
      • Slow key generation
      • Fast encryption and decryption
slide6

System Architecture

Key Generation

Select p, q p, q both prime, pq

Calculate n = pq

Calculate (n) = (p-1)(q-1)

Select integer e gcd((n),e) = 1; 1<e< (n)

Calculate d

Public key KU = {e, n}

Private key KR = {d, n}

Encryption

Plaintext : M < n

Ciphertext: C = Me (mod n)

Decryption

Ciphertext: C

Plaintext: M = Cd (mod n)

slide7

Primality

Test

gcd((n),e)

n = pq

(n) = (p-1) (q-1)

e, d

n

System Architecture

  • Key Generation

Random

Number

Generator

slide8

n

e, d

Modular

Exponentiation

m

C

System Architecture

  • Encryption
slide9

n

e, d

Modular

Exponentiation

C

m

System Architecture

  • Decryption
slide10

Implementation

  • Pseudo Random Number Generator
    • LFSR (Fibonacci configuration)
    • Length of the pseudo-random sequence depends on the length of the shift register and the number and position of the feedback taps.
slide11

Implementation

  • 512-bit Random Number Generator

RNG

512

seed

ce

512

output

reset_l

clk

slide12

Implementation

  • Modular Arithmetic
    • Modular Addition
      • concatenate 32-bit full adders
    • Modular Multiplication
      • binary method
    • Modular Exponentiation
      • binary method
slide13

Implementation

  • Addition
    • 16 clock latency for 512-bit adder
    • 32 clock latency for 1024-bit adder

512

a

512-bit

adder

ready

512

b

s_valid

c_in

512

s

start

c_out

reset_l

clk

slide14

Implementation

  • Modular Multiplication (512 bits and 1024 bits)

512

a

512-bit

mod_mul

512

b

ready

512

n

m_valid

start

512

m

reset_l

clk

slide15

Implementation

  • Modular Exponentiation (512 bits and 1024 bits)

512

a

512-bit

mod_exp

512

b

ready

512

n

e_valid

start

512

e

reset_l

clk

slide16

Request

KU

Testing

slide17

KU(m)

KR(KU(m))

Testing