Finite State Machine

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# Finite State Machine - PowerPoint PPT Presentation

1. Finite State Machine. Finite-state machine (FSM) model. A discrete system operates in a sequence of discrete steps E.g Model of a system that keeps track of the number of cars in parking garage each entry or departure is modeled as a discrete event. FSM- Notion of state.

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1

### Finite State Machine

Finite-state machine (FSM) model
• A discrete system operates in a sequence of discrete steps
• E.g Model of a system that keeps track of the number of cars in parking garage
• each entry or departure is modeled as a discrete event
FSM- Notion of state
• Intuitively, the state of a system is its condition at a particular point in time
• Formally, we define the state to be an encoding of everything about the past that has an effect on the system’s reaction to current or future inputs. The state is a summary of the past.
• Transitions between states govern the discrete dynamics of the state machine and the mapping of input valuations to output valuations

Visual Notation for FSM

The guard determines whether the transition may be taken on a reaction. A guard is a predicate

• The action specifies what outputs are produced on each reaction.
• An action is an assignment of values (or absent) to the output ports.
FSMD
• Visual Notation for FSMD

System interface

Partial English description

“Move the elevator either up or down to reach the requested floor. Once at the requested floor, open the door for at least 10 seconds, and keep it open until the requested floor changes. Ensure the door is never open while moving. Don’t change directions unless there are no higher requests when moving up or no lower requests when moving down…”

up

Unit

Control

down

open

floor

req

Request

Resolver

buttons

inside

elevator

b1

b2

...

bN

up1

up/down

buttons on each

floor

up2

dn2

up3

dn3

...

dnN

Example: An elevator controller

8

• Simple elevator controller
• Request Resolver resolves various floor requests into single requested floor
• Unit Control moves elevator to this requested floor
• Try capturing in C...

System interface

Sequential program model

Inputs: int floor; bit b1..bN; up1..upN-1; dn2..dnN;

Outputs: bit up, down, open;

Global variables: int req;

up

Unit

Control

down

void UnitControl()

{

up = down = 0; open = 1;

while (1) {

while (req == floor);

open = 0;

if (req > floor) { up = 1;}

else {down = 1;}

while (req != floor);

up = down = 0;

open = 1;

delay(10);

}

}

void RequestResolver()

{

while (1)

...

req = ...

...

}

open

floor

req

Request

Resolver

buttons

inside

elevator

b1

void main()

{

Call concurrently:

UnitControl() and

RequestResolver()

}

b2

...

bN

up1

up/down

buttons on each

floor

up2

dn2

up3

dn3

...

dnN

Elevator controller using a sequential program model

9

Finite-state machine (FSM) model

10

• Trying to capture behavior as sequential program is a bit awkward
• Instead, we might consider an FSM model, describing the system as:
• Possible states
• E.g., Idle, GoingUp, GoingDn, DoorOpen
• Possible transitions from one state to another based on input
• E.g., req > floor
• Actions that occur in each state
• E.g., In the GoingUp state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start = 0)

req > floor

GoingUp

!(req > floor)

timer < 10

req > floor

u,d,o, t = 1,0,0,0

Idle

DoorOpen

!(timer < 10)

u,d,o,t = 0,0,1,1

req == floor

req < floor

u,d,o,t = 0,0,1,0

u,d,o,t = 0,1,0,0

!(req<floor)

GoingDn

req < floor

Describing a system as a state machine

11

1. List all possible states

2. Declare all variables (none in this example)

3. For each state, list possible transitions, with conditions, to other states

4. For each state and/or transition, list associated actions

• 5. For each state, ensure exclusive and complete exiting transition conditions
• No two exiting conditions can be true at same time
• Otherwise nondeterministic state machine
• One condition must be true at any given time
• Reducing explicit transitions should be avoided when first learning

u is up, d is down, o is open

t is timer_start

FSM-UART
• Used for serial communication over serial port
• Baud Rate
• Start, Stop bits
FSM-Soda Machine
• Suppose you have a soda machine:
• When turned on, the machine waits for money
• When a quarter is deposited, the machine waits for another quarter
• When a second quarter is deposited, the machine waits for a selection
• When the user presses “COKE,” a coke is dispensed
• When the user takes the bottle, the machine waits again
• When the user presses either “SPRITE” or “DIET COKE,” a Sprite or a diet Coke is dispensed
• When the user takes the bottle, the machine waits again
Design FSM
• ATM Controller
• Traffic Light

With hierarchy

Without hierarchy

A

A1

z

A1

z

w

x

y

B

x

y

B

w

A2

z

A2

Concurrency

B

C

D

C1

D1

x

u

y

v

C2

D2

HCFSM and the Statechart language

15

• Hierarchical/concurrent state machine model (HCFSM)
• Extension to state machine model to support hierarchy and concurrency
• States can be decomposed into another state machine
• With hierarchy has identical functionality as Without hierarchy, but has one less transition (z)
• Known as OR-decomposition
• States can execute concurrently
• Known as AND-decomposition
• Statecharts
• Graphical language to capture HCFSM
• timeout:transition with time limit as condition
• history: remember last substate OR-decomposed state A was in before transitioning to another state B

fire

fire

fire

FireGoingDn

u,d,o = 0,1,0

fire

u,d,o = 0,0,1

floor==1

floor>1

FireDrOpen

With hierarchy

!fire

fire

UnitControl

NormalMode

req>floor

u,d,o = 1,0,0

GoingUp

!(req>floor)

req>floor

ElevatorController

u,d,o = 0,0,1

u,d,o = 0,0,1

Idle

DoorOpen

timeout(10)

req==floor

UnitControl

RequestResolver

req<floor

!(req>floor)

NormalMode

u,d,o = 0,1,0

GoingDn

...

!fire

fire

req<floor

FireMode

FireMode

fire

FireGoingDn

u,d,o = 0,1,0

!fire

u,d,o = 0,0,1

floor==1

floor>1

FireDrOpen

With concurrent RequestResolver

fire

UnitControl with FireMode

16

req>floor

UnitControl

• FireMode
• When fire is true, move elevator to 1st floor and open door

u,d,o = 1,0,0

GoingUp

!(req>floor)

req>floor

• w/o hierarchy: Getting messy!

u,d,o = 0,0,1

timeout(10)

u,d,o = 0,0,1

Idle

DoorOpen

req==floor

• w/ hierarchy: Simple!

req<floor

!(req<floor)

u,d,o = 0,1,0

GoingDn

req<floor

Without hierarchy

take

bottle

Idle

Dispense Product

Gather Cash

dispense

coke

q

q

q

cb

q

cd

25c

idle

25c

50c

dispense

diet coke

50c

Take bottle

cs

paid

dispense

sprite

take

bottle

cb

take

bottle

coke

cd

Diet

Coke

cs

Sprite

Exceptions
• Bottles can get stuck in the machine
• An automatic indicator will notify the system when a bottle is stuck
• When this occurs, the machine will not accept any money or issue any bottles until the bottle is cleared
• When the bottle is cleared, the machine will wait for money again
• State machine changes
• How many new states are required?
• How many new transitions?

take

bottle

OK

Stuck

Dispense Product

Idle

Gather Cash

dispense

coke

q

cb

q

cd

idle

25c

50c

dispense

diet coke

cs

dispense

sprite

take

bottle

take

bottle

cb

coke

cd

Diet

Coke

cs

Sprite

Hierarchical FSM

clear bottle

q

q

stuck

bottle

25c

50c

Take bottle

stuck

Clear

bottle

paid

Stuck

bottle

Capturing state machines in sequential programming language

20

• Despite benefits of state machine model, most popular development tools use sequential programming language
• C, C++, Java, Ada, VHDL, Verilog, etc.
• Development tools are complex and expensive, therefore not easy to adapt or replace
• Must protect investment
• Two approaches to capturing state machine model with sequential programming language
• Front-end tool approach
• Additional tool installed to support state machine language
• Graphical and/or textual state machine languages
• May support graphical simulation
• Automatically generate code in sequential programming language that is input to main development tool
• Language subset approach
• Most common approach...
Language subset approach

21

• Follow rules (template) for capturing state machine constructs in equivalent sequential language constructs
• Used with software (e.g.,C) and hardware languages (e.g.,VHDL)
• Capturing UnitControl state machine in C
• Enumerate all states (#define)
• Declare state variable initialized to initial state (IDLE)
• Single switch statement branches to current state’s case
• Each case has actions
• up, down, open, timer_start
• Each case checks transition conditions to determine next state
• if(…) {state = …;}

#define IDLE0

#define GOINGUP1

#define GOINGDN2

#define DOOROPEN3

void UnitControl() {

int state = IDLE;

while (1) {

switch (state) {

IDLE: up=0; down=0; open=1; timer_start=0;

if (req==floor) {state = IDLE;}

if (req > floor) {state = GOINGUP;}

if (req < floor) {state = GOINGDN;}

break;

GOINGUP: up=1; down=0; open=0; timer_start=0;

if (req > floor) {state = GOINGUP;}

if (!(req>floor)) {state = DOOROPEN;}

break;

GOINGDN: up=1; down=0; open=0; timer_start=0;

if (req < floor) {state = GOINGDN;}

if (!(req<floor)) {state = DOOROPEN;}

break;

DOOROPEN: up=0; down=0; open=1; timer_start=1;

if (timer < 10) {state = DOOROPEN;}

if (!(timer<10)){state = IDLE;}

break;

}

}

}

UnitControl state machine in sequential programming language

General template

22

#define S0 0

#define S1 1

...

#define SN N

void StateMachine() {

int state = S0; // or whatever is the initial state.

while (1) {

switch (state) {

S0:

// Insert S0’s actions here & Insert transitions Ti leaving S0:

if( T0’s condition is true ) {state = T0’s next state; /*actions*/ }

if( T1’s condition is true ) {state = T1’s next state; /*actions*/ }

...

if( Tm’s condition is true ) {state = Tm’s next state; /*actions*/ }

break;

S1:

// Insert S1’s actions here

// Insert transitions Ti leaving S1

break;

...

SN:

// Insert SN’s actions here

// Insert transitions Ti leaving SN

break;

}

}

}

VHDL Template

Architecture <arch_name> of <entity_name> IS

(Declaration of states and signals)

TYPE state is (state1,state2……...stateN);

SIGNAL present_state,next_state : state;

e.g. type states is (IDLE,STARTTX,BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7,STOPTX);

SIGNAL pr_state,nx_state : state;

Begin

---------------------------State Memory---------------------------------------------

PROCESS(reset,clock)

BEGIN

IF(reset=‘1’) then

pr_state<=state0;

ELSIF (clk’EVENT and clk=‘1’) THEN

pr_state<= nx_state;

END IF;

END PROCESS;

---------------------------------Next state and output logic ----------------------------------------

PROCESS(input, pr_state)

BEGIN

CASE pr_state IS

WHEN state0 =>

IF(input = …) THEN

output<=<value>

nx_state<=state1;

ELSE …

END IF;

WHEN state1 =>

IF(input = …) THEN

output<=<value>

nx_state<=state2;

ELSE …

END IF;

.

.

.

END CASE;

END PROCESS;

VHDL Template

process(pr_state,txData,enable)

begin

case pr_state is

when IDLE => tx<='1'; if(enable='1') then nx_state<=STARTTX; else nx_state<=IDLE; end if;

when STARTTX => tx<='0'; nx_state<=BIT0;

when BIT0 => tx<=txData(0); nx_state<=BIT1;

when BIT1 => tx<=txData(1); nx_state<=BIT2;

when BIT2 => tx<=txData(2); nx_state<=BIT3;

when BIT3 => tx<=txData(3); nx_state<=BIT4;

when BIT4 => tx<=txData(4); nx_state<=BIT5;

when BIT5 => tx<=txData(5); nx_state<=BIT6;

when BIT6 => tx<=txData(6); nx_state<=BIT7;

when BIT7 => tx<=txData(7); nx_state<=STOPTX;

when STOPTX => tx<='1'; nx_state<=IDLE;

end case;

end process;

VHDL Template
Verilog Template

---------------state memory------------

always @ (posedge clock)

pr_state<=nx_state;

---------------next state logic-------------

always @ (input,pr_state) begin

case(pr_state)

STATE1: if(input==…)

output=<value>;

nx_state=STATE2;

.

.

.