Networks on Chips: A New SoC Paradigm

1. Networks on Chips: A New SoC Paradigm Wendong Hu Bo-Kyung Choi Hyun J. Moon

2. Outline Introduction Challenges and Objectives Architecture � Topology Control � Protocol Software layers Conclusion

3. Challenges Technology scaling: complex systems on a chip possible. Designing challenges for complex SoC: Wire delay Power Signal integrity

4. Wire Delay Wires become �longer�, and wire delay becomes a performance bottleneck. Delay ~ L^2 Partition a long wire in segments with repeaters. Synchronization problem � leads to distributed systems on a chip

5. Power It costs more energy to send a bit of information over longer wires. To reduce delay, bigger drivers are used, which increase energy consumption Reduce voltage swing � good for performance and power, but requires special circuit technologies

6. Signal Integrity Growing capacitive and inductive coupling between wires. Large aspect ratio (H/W), and decreasing transition time. IR drop becomes significant as well. Differential signaling can help effectively.

7. Objectives Problem: Transmitting digital values on wires will be inherently unreliable and non-deterministic. Objectives: Predictable/scalable performance and signal robustness.

8. Requirements System-level architecture that scale with technology. Constructed from PBs (50k gates) not growing in complexity but in number with technology. A communication architecture allowing PBs cooperate efficiently

9. Requirements (ctd.) Ad-hoc global wiring by place & route tools Huge # of wiring with low usage. Need well controlled interconnect instead of ad hoc wiring. Along with transmitter/receiver, low-swing differential signaling.

10. Solution: Networks on a Chip Address interconnections on a chip as a communication problem. Apply techniques/approaches employed by large-scale communications and networking systems. Specifically, a protocol stack that isolates and organizes various functionality, performance, and reliability concerns.

11. Solution: Networks on a Chip (ctd.) Abstracted as communication channels with QoS setting vs. point 2 point wires Constraints:throughput/latency/correctness Dynamically route packetized data over a network vs. statically source to destination

12. Approach � Micro-network Overall design considerations The protocol stack (abstraction levels) Software (functional) Application/System Architecture and Control (logical) Transport Network Data link Physical wiring

13. Overall considerations (ctd.) Similar design requirements and constraints as of general networks. But, with distinctive characteristics Energy (communications) constraints a growing concern Vary frequency and voltage of nodes according to network bandwidth Design-time specialization Application specific Maintaining flexibility by reconfigurability

14. On-chip signal transmission Global wires Routed on the top metal layers Wider, thicker, more spacing Reduced voltage swing Not error-free Can be reduced or cancelled but costly Physical layer design Not to achieve ideal behavior But to satisfy competing metrics and provide channel abstraction to the above layers

15. Outline Introduction Architecture � Topology Control � Protocol Software layers Conclusion

16. Micronetwork Architecture Shared-medium networks Bus structure Direct & Indirect networks direct (point-to-point) interconnection router � network interface in computation unit indirect (switch-based) switch � provides programmable connections Hybrid networks

17. Shared-medium networks + simple, low-cost high utilization => prevalent in current SoCs - requires bus arbitration mechanism not scalable energy inefficient => not suitable for future SoCs with 10~100 units

18. Direct & Indirect networks use routers/switches to communicate provide scalability for large-scale designs performance depends on #ports, bandwidth, protocol, queue size, etc ~ 5GB/sec for 32 bit port in 100nm tech. cost ~ O(N2) area ( N : # of ports ) switch control logic queue size network interface module

19. Hybrid Networks Bus not scalable Switch network too expensive motivations for hybrid networks IP blocks underutilize the bandwidth network interfaces are expensive # switches can be significantly reduced

20. Hybrid networks ( cont�d ) Local communication on shared-medium bus packet-switched network on higher levels

21. Outline Introduction Architecture � Topology Control � Protocol Software layers Conclusion

22. Micronetwork Control Protocol stack is employed to effectively utilize micronetwork architecture Abstraction into data link layer, network layer and transport layer

23. Data Link Layer Requirement - To increase the reliability of the physical link up to a minimum required level Physical layer is not sufficiently reliable Packetizing data Performance vs. error probability tradeoff depending on packet size Error-correcting code alternating-bit, go-back-N and selective repeat

24. Network Layer Requirement � To implement end-to-end delivery control in network architectures with many communication channels Switching algorithms Circuit, packet and cut-through swithcing Routing algorithms Deterministic routing � good for regular traffic pattern Adaptive routing � good for irregular traffic (case of SoCs)

25. Transport Layer Requirement � To provide reliable end-to-end services (e.g. TCP) Packetization � at the source Resequencing and reassembling � at the destination Flow control and negotiation Deterministic approach � service quality guarantee with resource underutilization Statistical approach � more efficient but no quality guarantee

26. Future development on Micronetwork Control Further work to predict the tradeoff curves Architecture and protocol can be tailored to the target system or applications Impact of architecture and control design on communication energy consumption

27. Case of AEthereal Network-on-Silicon Research in progress (Philips) IP cores are connected by network Packet-switched router network Protocol stack-based design Provide guaranteed service Simplifies IP design and composition of IPs

28. Outline Introduction Architecture � Topology Control � Protocol Software layers Conclusion

29. Software Layer Network architecture and control layers Infrastructure Communications services to programmable end node Software layers System software Application software

30. System software System operation support Centralized control / distributed control Re-programmable for requirements Provide QoS with application constraints abstraction of underlying h/w platform DPM support Dynamic flow management support

31. Application software Support standard programming languages Dynamic binary code conversion Major goals for application sw development Portability across platforms Work with distributed platforms One strategy Programming interface between system and application software

32. Conclusion Despite numerous challenges, adequate solutions to the Complex SoC design probem will be found. Networks on a chip methodology will likely be the only path to mastering the complexity of SoC design.

33. References L. Benini, G. DeMicheli, "Networks on Chips: A new SOC paradigm�, IEEE Computer magazine, January 2002 P. Wielage, K. Goossens, "Networks on silicon: Blessing or Nightmare?�, Proceedings of the Euromicro Symposium on Digital System Design (DSD'02) K. Goossens et al., "Networks on silicon: combining best effort and guaranteed services�, Proceedings of the 2002 Design Automation and Test Conference and Exhibition, DATE 2002.