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WK 8. Basic I/O Interfacing. Objectives. Operation of basic I/O operations Decode 8-, 16, and 32-bit addresses for enabling I/O ports Handshaking for I/O operations Interface and program the 82C55 PPI (programmable peripheral interface)

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basic i o interfacing

WK 8

Basic I/O Interfacing

objectives
Objectives
  • Operation of basic I/O operations
  • Decode 8-, 16, and 32-bit addresses for enabling I/O ports
  • Handshaking for I/O operations
  • Interface and program the 82C55 PPI (programmable peripheral interface)
  • Using the 82C55 to connect LEDs, keyboards, etc. to the processor
  • Interface stepper and DC motors to the processor
  • Interface and program the 16550 programmable asynchronous serial interface adapter (UART)
  • Interface and program the 8254 programmable interval timer (PIT)
i o instructions
I/O Instructions
  • Two types:

- Transfer data between the processor accumulator (AL, AX, EAX) register and I/O device: IN and OUT

- Transfer string data between memory and I/O device directly: INSand OUTS (for processors above 8086)

IN and OUT:

  • The IN instruction (I/O Read): Inputs data from an external I/O device to the accumulator.
  • The OUT instruction (I/O Write): Copies the contents of the accumulator out to an external I/O device.
  • The accumulator is:

- AL (for 8-bit I/O),

- AX (for 16-bit I/O),

- EAX (for 32-bit I/O).

i o address
I/O Address
  • As with memory, I/O devices have I/O addresses (addresses for the I/O port)
  • Up to 64K I/O bytes can be addressed
  • The 16-bit port address appears on address bus bits A15-A0 This allows I/O devices at addresses 0000H-FFFFH
  • Two ways to specify an I/O port address:

- An 8-bit immediate (fixed) address (specified as a byte in the instruction): e.g. IN AX, p8 ; Reads a word from port p8

0000H-00FFH (can only see the first 256 addresses)

- A 16-bit address located in register DX (can be easily varied): e.g. OUT DX, AL; outputs the byte in AL to the port whose address is in DX

0000H-FFFFH (upto 16K addresses). i.e. high port addresses are accessible

only through DX addressing

DX

00FF

Immediate

i o data widths
I/O Data widths
  • As with memory, I/O ports are also organized as bytes
  • A port can be 1, 2, or 4 bytes wide (not 8 bytes wide on the Pentium)

Low Endian scheme:

Low address byte contains

low end (LS) part of data

Port is 4 bytes wide

00F3H

EAX

00F2H

Port is 2 bytes wide

00F1H

Port is 1 byte wide

AX

AL

Port Address p8

00F0H

LS byte

ins and outs i o instructions
INS and OUTS I/O instructions
  • They address I/O port using register DX
  • Transfer string data between port and memory

- INS: Moves string data to the Extra Segment;ES:DI

- OUTS: Moves data from the Data Segment;DS:SI

  • As with other string instructions, DI and SI can be automatically incremented or decremented depending on the state of the DF (direction flag) bit
  • Data width of transfer specified by using INSB, INSW, and INSD for byte, word, and double word
  • Can be prefixed with REP to repeat the instruction for a number of times stored in CX
slide7

(Note corrections)

Width of

Transfer

Determined

by the

‘A’ register

used

I/O Read

Width of

Transfer

Determined

by the

Instruction

used

DX

DX

DX

No argument,

DX by default

I/O Write

isolated vs memory mapped
Isolated vs. Memory Mapped
  • I/O can be either:

- Isolated, or

- Memory mapped

  • Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH)- isolated from the memory address space
  • Memory mapped I/O: uses memory reference instructions , e.g. MOV, and a region of the memory address map. So address space is shared between memory and I/O (used by only one of them)
  • Both techniques can be used with Intel processors
  • But most Intel-based systems e.g. the PC, use isolated I/O
  • Some other processors do not have dedicated I/O instructions and therefore use only memory-mapped I/O addressing, e.g. the PowerPC microprocessor (Macintosh computers)
slide9

Memory and I/O address

Maps for the 8086/8088

I/O Port specified

in DX, either explicitly or implicitly

Memory:

MOV

  • Isolated I/O
  • Using dedicated I/O
  • instructions e.g. IN, OUT

I/O:

IN

64 K

I/O bytes

00FF

Port specified immediately

as a byte in the I/O instruction

MOV

Range of memory addresses

assigned for I/O transfers

b. Memory-mapped I/O

Using ordinary memory

transfer instructions

e.g. MOV

Memory

the pc i o space
The PC I/O space
  • The PC I/O space mainly exists at locations below I/O port 0400H
  • Main board devices appear at addresses 0000H through 00FFH
  • Early ancillary I/O devices appear at I/O locations 0100H through 03FFH
  • Modern components appear at I/O locations above 0400H
  • The slide on the next page shows many of the I/O devices found in the personal computer
slide11

The PC I/O

Address Space

Processor communicates with and controls these peripherals through writing into/reading from their control registers accessed as I/O locations

03FF

Must use 16-bitvariable

I/O address in register DX

Reserved for use by

system components

and ISA bus

0100

00FF

Can Use either:

- Fixed (immediate) 8-bit

I/O address in instruction, p8

- Variable 16-bit

I/O address in register DX

Interval

(8254)

On Board Devices

0000

0000

in i o read
IN (I/O Read)
  • The IN instruction primarily takes he following forms:

IN AL,23H ;immediate

IN AL,DX ;DX holds address

IN AX,44H

IN AX,DX

IN EAX,2AH

IN EAX,DX

Data from the Input port addressed

is put on the data bus for the processor to read

into the A register

Size of data transferred in each case?

out i o write
OUT (I/O Write)
  • The OUT instruction primarily takes the following forms:

OUT 23H,AL ;immediate

OUT DX,AL ;DX holds port

OUT 4CH,AX

OUT DX,AX

OUT 1EH,EAX

OUT DX,EAX

Data from the A register is put on the data bus for

latching into the Output port addressed

Size of data transferred in each case?

in embedded systems most i o is 8 bits
In embedded systems, most I/O is 8-bits
  • To write the data 00H into Output port 62H

MOV AL,00H

OUT 62H,AL

or

MOV AL,00H

MOV DX,62H

OUT DX,AL

  • To read a byte from Input port address 71H:
  • IN AL,71H
  • or
  • MOV DX,71H
  • IN AL,DX
basic input port for i o reads
Basic Input Port (for I/O Reads)
  • The basic input port connects an external set of bits to the mP data bus whenever the mP executes the correct IN instruction with the correct I/O port address
  • External device puts data on the mP data bus

 Must include a 3-state (Tri-State) buffer to limit access to the processor data bus to the duration of executing the I/O instruction only

slide16

Basic 8-bit Input Interface:

Reads the status of 8 toggle

Switches (a byte read)

Pull-up

Resistors

To mP

Gate

Outputs:

Normally Hi-Z

Unless device is

Selected

(both G1 and G2 low)

0 1

Toggle switches

3-state buffer

The SEL signal is generated (active low)

By decoding:

- The address for the I/O port

- The I/O READ operation

Circuit can be expanded for

16-bit (word) or 32-bit (DWord)

interfaces

basic output port for i o writes
Basic Output Port (for I/O Writes)
  • The basic output port writes data from the mP data bus to an output port whenever the mP executes the correct OUT instruction with the correct I/O port address
  • Must latch the processor data put on the bus during the I/O instruction to make it available indefinitely for the port
  • No need for 3-state (Tri-State) buffers as the data bus is at the input side of the latch
slide18

Basic 8-bit Output Interface:

Controls 8 LEDs (1: OFF, 0: ON)

Circuit can be expanded for

16-bit (word) or 32-bit (DWord) interfaces

From mP

Edge-triggered

latch

OE

No HiZ.

O/P always

enabled

Data is latched and remains here until the next OUT

instruction to this port is executed

The SEL is generated (for + ive edge triggering) by decoding:

- The address for the I/O port

- The I/O WRITE operation

parallel port
Parallel Port
  • The parallel port is an example of interfacing slow devices, e.g. a printer, to the processor
  • A printer can print say 100’s of characters per sec (CPS), but the processor can output as many as 1000’s of CPS
  • To achieve ‘flow control’ and proper operation we use a technique called handshaking
  • Handshaking regulates the flow of data from the processor to a slower peripheral device to ensure correct operation
slide20

Computer (parallel port) has

  • a 25-pin DB25 connector
  • - Printer has a 36-pin Centronics
  • connector

Printer side

Computer side

Computer

Printer

Computer

Printer

Strobe Data

Into Printer

(STB)

Data

8-bit

Character data

Processor polls

‘Busy’ to see if

BUSY = 0 (printer not busy), so processor can send the data for next character

slide21

BUSY is the I/O address of the input port receiving the BUSY signal from printer

BUSY = 1: printer is busy printing- do not send a new character

BUSY = 0: printer is not busy - send a new character now

;An assembly language procedure that prints the ASCII data byte in register BL.

PRINT PROC NEAR

.REPEAT ;Poll the busy line until it goes low

IN AL,BUSY ;READ the port having the BUSY input

TEST AL,BUSY_BIT_MASK ;test if the Busy bit in the data read is 0

;BUSY_BIT is a mask defining the position

;of the BUSY bit in the port

.UNTIL ZERO ;End waiting loop if the ZERO flag is set

MOV AL,BL ;Yes!...move character data to AL

OUT PRINTER,AL ;and output it to printer-

;PRINTER is address of the printer port

;This also generates the #STB pulse

RET

PRINT ENDP

Loop repeatedly reads

BUSY & checks if it is low

Here

BUSY = 0!

So output

data to

Printer!

For example, if Busy goes on bit 4 of the BUSY port, BUSY_BIT_MASK will be:

00001000 and the instruction TEST AL, BUSY_BIT_MASK will AND AL

with the bit pattern 00001000. The result will be 0 only if the BUSY

Input is 0, setting the ZERO flag and ending the waiting (handshake Loop)

interfacing
Interfacing

When connecting external input and output devices to the

processor, we must take into account the DC characteristics

and drive capabilities of the mP pins, see Chapter 9

(Fan-out considerations

For outputs before)

mP

Output Devices, e.g.

LEDs

Input Devices, e.g.

Switches

mP Input

mP Output

Source

Sink

Source

Sink

input devices the switch

TTL Input

to mP

Input Devices: The Switch

= 5 V

  • The most basic input device
  • Switches are passive- do not produce a voltage, easily present a logic 0 to an I/P by grounding it.
  • To make a switch TTL compatible, a pullup resistor is used as shown. The value should be between 1K and 27K W.
  • Why not, say, 400 K W?
  • Switches bounce… and this is often undesirable.

Iin, High

(Single Pole

Single Throw)

The pullup resistor does

the conditioning required to

allow the switch to produce

a TTL compatible input to

the processor

Here, processor senses the switch

effect directly- hence bouncing

is a problem, especially if input

Is used as a clock

Wrong switch

State Can

be read

Here !

Final Posn

Initial Posn

the switch bouncing problem

TTL Input

to mP

The switch Bouncing Problem
  • Switch contacts bounce mechanically before it finally settles in the new position
  • With the simple arrangement shown, bounces can lead to the wrong input being read by the processor
  • The effect of switch bounces can be removed either:

 by Software, discussed later: Simply wait a little before reading the new switch status

 by hardware

  • Hardware solutions increase

circuit cost and complexity

switch de bouncing circuits
Switch De-bouncing Circuits

To

Processor

To Processor

  • Simpler, cheaper circuit
  • (inverters not NANDs)
  • - No pullup resistors required

1

1

Bouncing causes

 No Change from

New state

  • Processor now senses the output of a bistable flip flop (FF)
  • (with memory) controlled by the switch (not the switch directly as before)
  • Instantaneous change in the switch position causes a permanent
  • change in the FF output to the processor
  • A little bounce from the new position will not cause the FF to change state as
  • it remembers (through the feedback) the latest output before the bounce
slide26

Output Devices: The LED

  • LED diodes are used in many systems as indicators and as sources of infrared beams
  • LED must be forward biased to conduct and emit light
  • When conducting, a typical (Red, Green, or Yellow) LED passes a current of about 10 mA with a voltage drop Vdiode 1.65 V (1.5 V - 2 V in practice)
  • A Blue, White, or UltraBright LED passes more current at a larger voltage drop, e.g. 30 mA @ 2.5 V.

+

1.65 V

_

10 mA

A bit of electronics!

slide27

Interfacing the LED directly to a TTL O/P

  • 10 mA currents can be easily sunk by a TTL output at the low state (0)

(A standard 74 TTL O/P sinks up to 16 mA – lower values for lower power series e.g. 74LS sinks only 4 mA)

  • V out, low  0.1 V
  • V diode  1.65 V
  • To ensure I = 10 mA, R should be

= +5V

+

V diode

_

I min = 10 mA

R

V out

LED ON indicates 1 or 0 at Input?

Nearest standard

resistor value

slide28

Interfacing the LED through a transistor

Common

Emitter

  • If diode takes current > TTL sink current at the low state: Use a transistor to connect the LED
  • Transistor current gain (b= Ic/Ib  100) reduces current requirement from the TTL circuit (e.g. the mP or the buffer IC)
  • Ib = Ic/100 = 10mA/100 0.1 mA
  • Rc calculated as before, similar value
  • Rb should not

be larger than:

+

1.65 V

_

Ic = 10 mA

Ib = 0.1 mA

c

b

(TTL)

e

0.1V

Rb

0.7V

(Transistor

Is saturated)

Transistor:

b = Base

e = Emitter

c = Collector

Use minimum gain value specified

(worst case condition)

Nearest standard

resistor value

driving larger currents and voltages e g dc motors mechanical relays etc
Driving larger currents and voltages; e.g. DC motors, mechanical relays, etc.
  • Large current loads such as motors or large relays require a Darlington pair in place of the transistor driver
  • Two transistor gains in cascade, (b = b1 b2), so smaller base currents from TTL for large load currents
  • Can use 12 V or higher supply
  • Select a transistor that meets both the voltage and current requirements for the load
  • The diode is used to prevent the transistor from being destroyed by the inductive kickback current that appears when the field collapses suddenly in the coil

Current can not change instantly through

an inductor. If it suddenly drops from I1 to 0, a negative current - I1 is generated which gradually decays to 0. The diode provides a safe path for this current away from the transistor

12 V

DC Motor

Ic = 1 A

Rb

(TTL)

0.7V

0.7V

Diode off

In normal

operation

1A/(7000)=0.143 mA

b = b1 b2

port address decoders

WK 9

Port Address Decoders
  • As with memory addresses, port addresses must also be decoded to select an I/O device for a particular port number.
  • Memory mapped I/O is identical to memory access (with IO/#M = 0)
  • Will consider here only isolated I/O (using dedicated instructions: IN, OUT, etc.)
  • Most embedded systems use only fixed I/O addressing:

- i.e. Only the least significant eight address bits A7-A0 are decoded. Limits number of I/O ports to 256 (enough)

  • PC systems used fixed/variable I/O addressing:

- All 16-bits of the I/O address A15-A0 are decoded, allowing the use of up to 64K ports

  • Decoding is simpler than for memory- smaller # of address lines
  • Isolated I/O transfers are activated using (depending on processor and mode):

- IO/#M = 1, M/#IO = 0, #IORC, #IOWC, #RD, #WR, W/#R

address decoding for 8 i o ports f0 to f7 for the 8088 using 8 bit i o address
Address Decoding for 8 I/O Ports: F0 to F7for the 8088 using 8-bit I/O address

a. Using a Decoder IC

Decoder O/Ps

Decoder I/Ps

X

X

X

0

1

1

1

1

X

X

X

1

0

1

1

1

LS part

(Select port

on decoder)

To ‘Enable’

Inputs on the

8 I/O ports

MS part

(Enable decoder)

A7 …....A0

3-to-8

Decoder

11110000 = F0 1st

11110001 = F1 2nd

…………………….

11110111 = F7 7th

Address from mP

Note: #IO/M decoding should be added

slide32

A7 …....A0

11110000 = F0 1st

11110001 = F1 2nd

…………………….

11110111 = F7 7th

b. Using a PLD

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_11 is

port (

A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;

D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_11 is

begin

D0 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0 );

D1 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0 );

D2 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0 );

D3 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0 );

D4 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0 );

D5 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0 );

D6 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0 );

D7 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0 );

end V1;

Outputs are

active low

I/O control not decoded

address decoding for 8 i o ports for the 8088 with 16 bit i o address
Address Decoding for 8 I/O Ports:for the 8088 with 16-bit I/O address

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_12 is

port (

Z, A12, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;

D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_12 is

begin

D0 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and not A2 and not A1 and not A0 );

D1 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and not A2 and not A1 and A0 );

D2 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and not A2 and A1 and not A0 );

D3 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and not A2 and A1 and A0 );

D4 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and A2 and not A1 and not A0 );

D5 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and A2 and not A1 and A0 );

D6 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and A2 and A1 and not A0 );

D7 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and

A4 and A3 and A2 and A1 and A0 );

end V1;

Note: I/O control not decoded

I/P

Z = not (A15 & A14 & A13 & A11)

16 I/Ps

Check:

#(1110111111111011)

= #EFFBH

16 bit wide i o 8086 286 386sx
Same with memory banks, we have multiple I/O byte banks (each 1 byte)

For processors with a 16-bit data bus: 2 banks (for low and high bytes)

64K 8-byte I/O ports  32K 16-bit ports (decoded using most significant 15 bits of the 16-bit I/O address)

Which byte in the port is determined by the LSB (A0) and the #BHE:

For I/O writes, as with memory, use separate strobe signals (e.g. #BLE or #BHE) for the separate byte ports

For reads, normally no action is required as processor reads the byte it wants. This is OK assuming the port responds correctly to the read command from the processor

16-bit Wide I/O: 8086,286, 386SX

64K Byte Ports

32K Word Ports

LS byte port

MS byte port

16-bit (Word) port: Port # starts with A1 not

A0 (15 lines  215 = 32K 16-bit ports)

A0 goes through 1 and 0  it is a don’t care

byte selection in a 16 bit port
Byte Selection in a 16-bit port

Enabled with #BHE

Enabled with #A0

slide36

Byte (bank) selection for Writes only… i.e. for OUT ports only

16-bit Output Port which allows

the processor to write

into either or both

its two separate bytes

mP

Data Bus

A7

A1

40H = 0100 0000 (mostly zeros  use OR function)

D0 = A7+#A6+A5+A4+A3+A2+A1+A0+ #IOWC

I/O Write

Start with A1

Low Byte Port

Strobe mP Data In

Similar to memory,

Data is written into port

at the rising edge of #WR

Width

Determine by

Narrowest

Signal

Which is?

This part

Is the same

For both byte ports

Strobe mPData In

41H = 0100 0001

High Byte Port

D1 = A7+#A6+A5+A4+A3+A2+A1+ #BHE + #IOWC

Output always enabled:

Tri-state feature is not utilized

Not required for output ports

D8

Start with A1

slide37

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_14 is

port (

BHE, IOWC, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;

D0, D1: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_14 is

begin

D0 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or A0;

D1 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or BHE;

end V1;

slide38

16-bit Input Port: No use of BHE or A0

(Processor knows which byte it wants)

Buffers must be Tri-State

Because their outputs connect to the

Processor data bus!

mP

Data Bus

No A0 or BHE

Dropped A0

I/O Read

Common Strobe for both byte ports

(No byte selection for READs)

Allow External Data In

(No latching)

7-bit address

7-bit address lines

27 = 128 x 2-byte ports (= 256 byte ports)

Simple buffers not latches- Data is available

For long time at I/P

slide39

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_15 is

port (

IORC, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC;

D0: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_15 is

begin

D0 <= IORC or A7 or not A6 or not A5 or A4 or A3 or not A2 or A1;

end V1;

A0

1

1

0

0

1

0

0

0

1

Lower Byte: 64H

Higher byte: 65H

The lowest 8-bit address (64H) is used by the software

to address this 2-byte port for all READs from its two bytes

32 bit wide i o e g for 80486
32-bit Wide I/O, e.g. for 80486
  • The only difference between 16-bit wide I/O and 32-bit wide I/O is that 32-bit wide I/O consists of 4 side-by-side 8-bit ports instead of 2.
  • Same as with memory interface: for each doubling of the number of byte ports connected to the data bus  drop one more of the LS address bits
  • So with 80486 we (32-bit data bus) we drop A0 and A1
  • Next slide illustrates a 32-bit wide input port that decodes only 6 bits of address.
slide42

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_16 is

port (

IORC, A7, A6, A5, A4, A3, A2: in STD_LOGIC;

D0: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_16 is

begin

D0 <= IORC or A7 or not A6 or not A5 or not A4 or A3 or A2;

end V1;

A1 A0

(not decoded)

0 0

0 1 1 1 0 0

70H

0 1

Determine the 4 addresses of the four byte ports and

Verify you get addresses given on the previous slide

1 0

1 1

The lowest 8-bit address (70H) is used by the software

to address this 4-byte port

i o for the pentium
I/O for the Pentium
  • Although the Pentium has a 64-bit data bus, only memory transfers use it
  • I/O instructions support a maximum of 32 bit transfers, i.e. over a max of 4-byte ports

(EAX is 32 bits!)

  • Pentium has 8 byte enable signals BE0, …, BE7 to allow selecting the byte to be written into a memory bank
  • For I/O, we will use them to select which I/O byte bank to write into for output ports
  • Which bank to read from an input ports is left to the processor (no hardware bank selection for READS)
  • The bank number is determined by the LS 3 bits of the byte address (replaced by the 8 BEi signals)

Pentium 8 byte banks.

I/O uses a max of only

4 banks at a time

XX111

XX110

XX101

XX100

XX011

XX010

XX001

XX000

i o for the pentium1
I/O for the Pentium

Still 16-bit address

for I/O

  • Examples:
  • Byte port 0034H:
  • 00110100  Bank 4
  • (i.e. Use BE4)
  • 2-Byte port 005CH-005DH:
  • 01011100-01011101  4,5
  • (Use BE4, BE5)
  • - 4-byte port 0104H-0107H:
  • ….0100-….0111  4,5,6,7
  • (Use BE4,BE5,BE6,BE7)

XX111

XX110

XX101

XX100

XX011

XX010

Invalid 32-bit port

XX001

XX000

Two valid 32-bit ports (22 bytes):

Moving within the port changes only the 2 LSBs of the address

Any bank can be a byte port

Four valid 16-bit ports (21 bytes):

Moving within the port

changes only the LSB of the address

Invalid 16-bit port

slide45

Byte 0

Byte 1

2-byte Output (Write) port for the

Pentium at addresses

2000H and 2001H:

….0000-….0001  Banks 0,1

(i.e. use BE0, BE1)

Determine which

BEs to use from

LS 3-bits of address

A2-A0

A2-A0 Dropped

Bank 0

(BE0)

Outside

World

mP Data Bus

Bank 1

(BE1)

slide46

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_17 is

port (

MIO, BE0, BE1, WR, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4,

A3: in STD_LOGIC;

D0, D1: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_17 is

begin

D0 <= MIO or BE0 or not WR or A15 or A14 or not A13 or A12 or A11 or A10

or A9 or A8 or A7 or A6 or A5 or A4 or A3;

D1 <= MIO or BE1 or not WR or A15 or A14 or not A13 or A12 or A11 or A10

or A9 or A8 or A7 or A6 or A5 or A4 or A3;

end V1;

the 82c55 ppi
The 82C55 PPI

PPI = Programmable Peripheral Interface

  • The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports
  • The PC uses a few 82C55 (in the chip set) to control the keyboard, speaker, and parallel port
  • The 8255 PPI is available in DIP or surface mount forms
  • Also implemented as functions within modern interface chip sets
slide48

3 programmable

8-bit I/O ports: A, B, C

Similar to a 4-byte

RAM

2 Groups

12-bit groups A, B

A

Data Bus

Port A + Upper half of C = Group A

(12 bits)

2-bit Address I/P

(select port or

Command register

for Read or Write)

B

Read/Write

Control

Port B + lower half of C = Group B

(12 bits)

CS

Input

(low)

  • On the PC: Two 82C55s
  • One 82C55 occupies
  • 4 I/O ports 60H-63H:
  • Handling Keyboard, timer,
  • speaker, etc.
  • One 82C55 occupies
  • 4 I/O ports 378H-37BH
  • Parallel printer port

C

RESET initializes the PPI to operate

in mode 0 & all 3 ports as inputs

at power up.

With all ports as input ports,

this avoids damage to the device at

Power up

82C55 DIP Version

i o port assignments
I/O Port Assignments
  • Group A is Port A and upper ½ of Port C (PC7-PC4).
  • Group B is Port B and lower ½ of Port C (PC3-PC0).

Writing into this register

programs the various ports to operate in

various modes and be used

as either inputs or outputs

slide51

Address from microprocessor

A1 A0 Inputs on 82C55

  • A7 A6 A5 A4 A3A2 A1A0
  • 1 0 0 0 0 0 0 = C0H Port A
  • 1 1 0 0 0 0 1 0 = C2H Port B
  • 1 1 0 0 0 1 0 0 = C4H Port C
  • 1 0 0 0 1 1 0 = C6H Comnd
  • Register

80386SX Processor

Select PPI

At decoded

mP address

1

0

0

001

1

0

0

Address from

80386SX

microprocessor

programming the 82c55
Programming the 82C55

Program

  • Using one internal register
  • If bit 7 = 1 select format for Command Byte A
  • If bit 7 = 0 select format for Command Byte B
  • Bit 7 = 1: Command Byte A:
  • Programs Groups A and B (as defined
  • in terms of ports A, B, C - previous slide):
  • - as either inputs or outputs
  • - in either modes 0, 1, or 2

Only for mode 0

Program

  • Bit 7 = 0: Command Byte B:
  • Sets (to 1) or Clears (to 0) the specified one
  • of 8 bits of port C (in modes 1 and 2)
8255 modes
8255 Modes

Data

  • Mode 0 (for groups A & B)- the most commonly used mode: All 12 bits of the group are simple inputs or simple latched outputs
  • Mode 1 (for groups A & B)- is used occasionally to provide handshaking to an I/O device and operate asynchronously with the device. Most Port C bits are dedicated for handshake functions for the operation. A few are controlled separately using the Command byte B format for handshaking I/O.
  • Mode 2 (for group A only- Group B not used)- is a bidirectional mode for Port A only (Port B is not used). Port C provides handshaking signals.

Data

Data

Control,

e.g. Busy, Strobe, etc.

slide54

8255 Modes

When O/P,

Set or Reset

Using

Command Byte B

Control:

Handshaking

For the data port

Not

Used

programming the 82c551
Programming the 82C55
  • To program the command

register of the 82C55 and select operation use command byte A

  • For example, to program all the ports as outputs and in mode 0 (the most common mode) use:

MOV AL,80H

MOV DX,COMMAND_PORT

OUT DX,AL

= C6H in slide 50

7 segement display
7-Segement Display

CA

 Vcc

Anode

Cathode

Select Segments: Switched Resistors to GND

CC

Select Segments: Switched Resistors to Vcc

 GND

7 segement display1
7-Segement Display

Anode

Cathode

Segment Data (1 byte)

for each character

multiplexed 7 segement display
Multiplexed 7-Segement Display

Common

To segment

on all Digits

  • Motivation for MUXing:
  • Reduce the number of segment drivers
  • by a factor of n

n = 8

Digits

Sequentially

Turn ON one digit at a time

Recommended rate: 100 – 1500 times per sec

slide60

Address decoding is similar to

that of a 4-byte Read/Write memory

1 turns

segment ON

Tr 1

Most Significant

(MS) Digit

Tr 2

A: O/P Port:

Segment data

For selected digit

Multiplex the eight digit displays

(only one is ON at a time)

0 turns digit

digit ON

Vcc

B: O/P Port:

Select # Displayed

B: O/P Port:

Select digit

To be displayed

1 digit

Digit transistor switch

Controlled by Port B bit,

e.g. Tr 1

. . . . . .

GND

PLD for 14-bit

I/O address (A15-A2) + IO/#M decoding

7 Segment data transistor switches

Controlled by Port A bits, e.g. Tr 2

slide61

PLD Program for Address Decoding

library ieee;

use ieee.std_logic_1164.all;

entity DECODER_11_21 is

port (

IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3,

A2: in STD_LOGIC;

D0: out STD_LOGIC

);

end;

architecture V1 of DECODER_11_17 is

begin

D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10

or not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2;

end V1;

82C55

4 I/O ports:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 1 1 1 0 0 0 0 0 0 X X

0700 Port A

0701 Port B

0702 Port C

0703 Control

Register

Total: 16-bit I/O

address

14-bit address decoding

Using PLD

On chip

Selection

slide62

; Program the 82C55 for Port A and Port B are output ports in mode 0

MOV AL, 80H ; 80H Data into AL

MOV DX, 703H ; Address of Command Port into DX

OUT DX, AL ; Write 80H into Command Port

; ; to program PPI

; An assembly language procedure that multiplexes the 8-digit display.

; This procedure must be called often enough for the display to appear stable

DISP PROC NEAR USES AX BX DX SI

PUSHF

MOV BX,8 ;load counter BX with # of display digits

MOV AH,7FH ;load initial digit selection pattern to enable MS digit (01111111)

MOV SI,OFFSET MEM - 1 ;Load SI with offset (MEM) - 1

MOV DX,701H ;address Port B (for Port A: decrement DX)

;Sequentially display all 8 digits starting with MS digit

.REPEAT

MOV AL,AH

OUT DX,AL ;send digit selection pattern to Port B

DEC DX ;Address Port A (to send Digit Data)

MOV AL,[BX+SI] ;Load digit data from memory into AL

OUT DX,AL;send digit data to Port A

CALL DELAY ;wait 1.0 ms leaving displayed digit ON

ROR AH,1 ;adjust selection pattern to point to next digit

INC DX ;Address port B

DEC BX ;decrement counter for data of next digit.

.UNTIL BX == 0

POPF

RET

DISP ENDP

8 bytes of

Digit Data

In memory

MS Digit

MEM+7

.

.

.

BX

MEM

LS Digit

Procedure for 1 ms delay, e.g. a loop of instructions

i.e. digit remains ON for 1 ms before moving to next

slide63

; Delay Loop

DELAY PROC NEAR USES CX

MOV CX, XXXX ; XXXX determines delay, = Delay required / loop exec time

D1:

LOOP D1

RET

DELAY ENDP

Loop execution time is calculated from instruction data and the clock frequency.

An 80486 executes “LOOP D1” in 7 clock cycles

With a 20 MHz clock, loop exec time = 7 x 50 = 350 ns

XXXX = 1ms/350ns

Display Flashing Rate:

- Assume the DISP Procedure is called continuously

- Ignore loop execution times relative to delay time (e.g. 350 ns << 1 ms)

1 ms

DISP Proc

DISP Proc

. . .

. . .

. . .

Digit Displayed

1

1

2

2

7

7

8

8

8 ms

Flashing rate = 1/8 ms = 125 Hz

slide64

Stepper Motor Interface

Wk 10

2 coils

driven at a time

45

135

  • Stepper motor is digital in nature
  • It rotates in a sequence of discrete steps controlled by sequentially energizing a set of coils (windings)
  • Step angles vary from 1 to 15  depending on precision required (and cost)

Anti-clockwise Rotation

  • N Pole lies between the two energized coils
  • Rotation Direction: Anti-clock wise
  • Step angle: 90

225

315

ROL: Motor rotates anticlockwise

0

1

0

1

ROR reverses the direction of

Motor rotation

slide65

1 activates coil

Darlington pairs

for driving

high load currents

Anti-surge diodes

ROL

Rotate instruction operates on whole byte

We want to rotate half the byte duplicate pattern!

33H = 00110011

66H = 01100110

CCH = 11001100

99H = 10011001

ROL

ROR

Current angular

Position stored at location

POS (in memory)

POS

33H or 66H or CCH or 99H

Clockwise

Anti-Clockwise

slide66

PORT EQU 40H

;An assembly language procedure that controls the stepper motor

STEP PROC NEAR USES CX AX

MOV AL,POS ;get position

OR CX,CX ;set flag bits

IF !ZERO?

.IF !SIGN? ;if not sign  Rotate left

.REPEAT (anti clockwise)

ROL AL,1 ;rotate step left

OUT PORT,AL

CALL DELAY ; wait 1 ms for motor to move

.UNTILCXZ

.ELSE

AND CX,7FFFH ;make CX positive

.REPEAT

ROR AL,1 ;rotate step right

OUT PORT,AL

CALL DELAY ;wait 1 ms for motor to move

.UNTILCXZ

.ENDIF

.ENDIF

MOV POS,AL ; Save POSN for next step

RET

STEP ENDP

  • CX has:
  • Sign of rotation
  • 0: ACW 1:CW
  • # of steps
  • e.g. 0000H (0)
  • 0005H (5,ACW)
  • 8007H (7,CW)

Not

CX Positive: Rotate Anti-clockwise

CX Negative: Rotate Clockwise

If CX = 0 Quit

No rotation

required

At exit of proc, CX is changed

slide67

Interfacing a 4x4 Key Matrix

Row Inputs

I/P

Y

O/P

X

0

0

0

0

Column Outputs

1. All 0’s

To check

For any

Press/Release

2. Scan columns with

one 0 to locate a

pressed key

0

  • With no keys pressed, all row inputs are 1’s
  • due to the pull up resistors connected to Vcc
  • Column outputs are sequentially scanned as 0’s
  • If key (X,Y) is pressed, it connects the scanning
  • 0 from column X output to row Y input. If no other key
  • is pressed on the same column, this allows the pressed
  • key to be identified.
slide68

Wait for any remaining

pressed keys

to be Released

Wait for next key to be

Pressed to determine it

Scan for the next key pressed

and locate its column

Still

Software Debounce

Of Switch Release

Software Debounce

Of Switch Press

Scan again after things have settled, and determine coordinates (row, column) of pressed key



Here, column is known

Read Input Pattern

into CF

Determine row of key pressed

(look for 0 bit in read data)

row

Use key position determined

To get its corresponding

Code stored in a lookup table

In memory

slide69

;assembly language version;

;KEY scans the keyboard and returns the key code in AL.

COLS EQU 4

ROWS EQU 4

PORTA EQU 50H

PORTB EQU 51H

KEY PROC NEAR USES CX BX

MOV BL,FFH ;compute row mask

SHL BL,ROWS

MOV AL,0

OUT PORTB,AL ;place all zeros on Port B

.REPEAT ;wait for release

.REPEAT

CALL SCAN

.UNTIL ZERO?

CALL DELAY10 ; Release debounce

CALL SCAN

.UNTIL ZERO?

.REPEAT ;wait for key press (to be determined)

.REPEAT

CALL SCAN

.UNTIL !ZERO? ; (not zero, i.e. not = FF)

CALL DELAY10 ; Press debounce

CALL SCAN , scan again after things have settled

.UNTIL !ZERO?

MOV CX,00FEH

.WHILE 1 ;find column

MOV AL,CL

OUT PORTB,AL

CALL SHORTDELAY ;Wait till data outputted to PortB have settled!

CALL SCAN

.BREAK !ZERO? ;Key found at this column- Quit WHILE1!

ADD CH,COLS ;Key not found at this row- move on to next row – add COLS to CH

ROL CL,1 ;AL = 11111101 on 2nd trial

.ENDW

.WHILE 1 ;find row from pattern Read into PortA in SCAN

SHR AL,1

.BREAK .IF !CARRY? ; LSB of AL is shifted into the carry flag by SHR! So we stop on 1st zero bit

INC CH ; for each shift until row is found

.ENDW

MOV AL,CH ;get key code into AL: AL = CH = (COLS)X + Y = 4 X + Y; X = 0, 1,..,3 , Y = 0, 1,.., 3

RET

KEY ENDP

SCAN PROC NEAR

IN AL,PORTA ;read rows

OR AL,BL

CMP AL,0FFH ;test for no keys

RET

SCAN ENDP

  • Program the 8255 for:
  • Port A: Input
  • Port B: Output
  • Size in ROWS, COLS can
  • be set, up to 8 x 8, here 4 X 4

BL = F0, for rows = 4

Mask for Oring in SCAN

Keep calling SCAN

Until FF (no key pressed)

i.e. wait for key release

Keep calling SCAN

Until (Not FF) (a key pressed)

i.e. wait for key stroke

1st Column

AL = 11111110

Y

(row)

X (Column)

Determine

X,Y of

Pressed

Key as

Number

In CH  AL

AL from SCAN

(for a key pressed on row 3)

After SCAN:

AL = XXXX1011

Column #

Row #

ASCII?

SHR into Carry

BL: 11110000 = F0H

AL: XXXX1111 (No Keys Pressed)

Oring: 11111111 = FF

ZERO: No Pressed

!ZERO: Pressed

mode 1 port a b for strobed input
Mode 1: Port A/B for Strobed Input

as Input

as Input

To mP

Port

Latch

mP Data

Bus

Data Byte

  • Ports A and/or B used as latching input ports to store data temporarily from external devices before processor is ready to take the data in.
  • Port C provides the control (handshake) bits:

- PC5(1): IBF (Input buffer full) Output indicating (to both external device and mP) if port latch has data

- PC4(2):#STB (strobe) Input latches data into the port latch at the + ive going edge

- PC3(0): INTR (Interrupt Request) If enabled, used to interrupt the processor. High at + ive going edge of #STB and low after data is read by processor

- PC4(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation

- PC6,7 General Purpose I/O bits. Set/Reset by CBB

2

E x t e r n a l B u s

1

to Dev & mP

Handshake

mP

(Normal I/O bits)

Program with Command Byte B (CBB) format

For Input Operations…Action started by who?

Automatically the associated C half assumes

these functions- no longer separately

Programmed (except PC6,7)

Software Polling by mP

automatic

Release IBF

For next

transfer

IBF = 1

  • Two ways to interface to the processor:
  • Polled: Processor polls IBF waiting for
  • data to be available in port latch (IBF=1)
  • Interrupt-driven: INTR is used to
  • interrupt the processor when data
  • becomes available in port
  • - saves processor time

Hardware Polling

By Device

or

(If Enabled)

automatic

External Device

Side

Microprocessor

Side

Data from External Device

microprocessor reads data

from port latch through the data bus

Data strobed in from

external device into port latch

interfacing a keyboard to m p using port a in mode 1 strobed input
Interfacing a Keyboard to mP using Port A in Mode 1 (Strobed Input)

Handshake (Polling) Method

;A procedure that reads the keyboard and

;returns the ASCII key code in AL

BIT5 EQU 20H ;00100000 Mask defining PC5 (IBF for Port A)

PORTC EQU 22H

PORTA EQU 20H

READ PROC NEAR

.REPEAT ;poll IBF bit

IN AL,PORTC

TEST AL,BIT5

.UNTIL !ZERO? ; Quit polling when bit 5 read is not ZERO (IBF=1)

IN AL, PORTA ; get ASCII value of key pressed from keyboard

RET

READ ENDP

Port A

  • 8255 should be programmed for operation in:
  • Group A in Mode 1
  • - Port A is input

Data

To Processor

H/S Control (PC5 IBF bit)

Port C

1 ms

mode 1 port a b for strobed output

Data from mP

Is strobed into port latch

at trailing edge of #WR

from mP

by mP

Mode 1: Port A/B for Strobed Output

Port Latch

Data Byte

From mP

mP Data

Bus

  • Ports A and/or B used as strobed output ports to write data from processor into external devices. Associated half C bits provide handshake signals for the interface.
  • Port C provides control bits:

- PC7(1): #OBF (Output Buffer Full) Activated when port has data written into it by the processor. Deactivated to 1 when #ACK is received from external device indicating that data was read.

- PC6(2): #ACK (Acknowledge input) from external device requesting data in port to be put on external bus for reading by external device

- PC3(0): INTR (Interrupt Request) Used to interrupt the processor when external device receives data (end of #ACK).

- PC6(2) INTE (Interrupt Enable) Internal bit programmed through PC4(2) for enabling/disabling interrupt generation

- PC4,5 General Purpose I/O bits

2

External Bus

1

Handshake

Automatically the associated C half assumes these functions- no longer separately programmed (except PC4,5)

For output operations…Action started by who?

  • Again mP can do its part
  • in two ways:
  • Polling for #OBF high
  • Getting an interrupt
  • with INTR

Hardware Polling by

Device

Software Polling

By Processor

or

Automatic

Automatic

Device

Realizes there is

Data in port latch

(If Enabled)

For mP to O/P

Next char

Microprocessor

Side

External Device

Side

  • For device to take data:
  • #ACK puts latch data on the external bus
  • mP Provides a strobe pulse
interfacing a printer to m p using port b in mode 1 strobed output

Reset PC4

Set PC4

1 0 0 0

1 0 0 1

In port C

Interfacing a Printer to mP using Port B in Mode 1 (Strobed Output)

;A procedure that transfers an ASCII character from AH to the printer

;connected to port B

BIT1 EQU 2 ; Bit PC1 = #OBF for port B

PORTC EQU 62H

PORTB EQU 61H

CMD EQU 63H; The 8255 command byte address

PRINT PROC NEAR

.REPEAT ;Wait for printer ready to receive a new char- Poll #OBF till high

IN AL,PORTC

TEST AL,BIT1

.UNTIL !ZERO? ; #OBF =1 No data in output buffer, so can write into it!

MOV AL,AH ; Write ASCII char data into port latch

OUT PORTB,AL

MOV AL,8 ;Generate data strobe pulse

; on PC4

OUT CMD,AL

MOV AL,9

OUT CMD,AL

RET

PRINT ENDP

mP Polling for #OBF = 1

Data from mP to

port latch

Port B

Data from port latch

to Printer

Data

Control (PC1 #OBF bit)

Ordinary C I/O bit

Set and reset with command byte B

To generate the #DS pulse (Strobe output) signal to Ex Device

Strobe data

Into Printer

Port C

#OBF not used

As a strobe to printer

mode 2 port a only for bidirectional i o
Mode 2: Port A only for Bidirectional I/O
  • Ports A (only) is used for bidirectional I/O. 5 Port C bits provide bidirectional handshake signals. 3 Port C bits are programmable I/O with Command byte B format.
  • Application: Computer-to-computer comm., GPIB bus
  • Handshake signals combine input handshake and output handshake of mode 1:

- For Input: #STB, IBF

- For Output: #OBF, #ACK

- Common: INTR (qualified by 2 internal enable bits INTE1 and INTE2)

  • Program operates the port’s bidirectional bus using the OUT and IN instructions

O/P Control

To/From mP

I/P Control

mode 2 example processor sends data to external device on the bidirectional bus
Mode 2 Example: Processor Sends Data to External Device on the Bidirectional Bus

To send Data from processor to external device:

1. Processor checks if #OBF = 1 (No data pending in port)

2. Processor OUTs data to port (Writes it into Port A latch- not on external bus yet)

3. Port automatically lowers #OBF O/P to alert device to take data

4. Device detects 3 and lowers #ACK input to port

5. This raises #OBF high

6. #ACK enables Port external bus to carry latch data so it can be taken by device

7. After device takes data it raises #ACK high

O/P Control

From mP

I/P Control

;A procedure transmits AH through the bidirectional bus

BIT7 EQU 80H

PORTC EQU 62H

PORTA EQU 60H

TRANSPROC NEAR

.REPEAT

IN AL,PORTC

TEST AL,BIT7

.UNTIL !ZERO?

MOV AL,AH

OUT PORTA,AL

RET

TRANS ENDP

I understand you have

data for me in your latch.

Please put it on the bus

so I can take it!

Wait for #OBF =1

Result = 1 (Not zero)

2

5

1

3

7

4

Data in Port A latch,

but not on its I/O bus yet

Port I/O bus

is normally HiZ

To allow use in

The other direction

Enable

I/O Bus

to carry

latch data

6

By external device

(May need a strobe pulse from mP)

By Microprocessor

mode 2 example processor receives data from external device on the bidirectional bus
Mode 2 Example: Processor Receives Data from External Device on the Bidirectional Bus

To Receive Data:

1. External device sending data checks if #IBF = 0 (No pending data in port latch not read by processor) (Hardware Polling)

2. Then it puts its data on external bus and strobes it into port latch using #STB

3. IBF automatically goes high until data is read by processor

4. Processor polls IBF for IBF = 1 to make sure data is in port latch (software polling)

5. Processor reads data from port

6. This automatically lowers IBF to enable further writes

O/P Control

To mP

I/P Control

Hardware Polling for IBF = 0 by device to generate #STB

To avoid overwriting existing data in Port not read by processor yet

2

1

3

4

6

Port I/O bus

is normally HiZ

2

Step 4

5

Step 5

latch

HiZ external bus!

(It is OK…

processor reads

its data bus)

READ PROC NEAR

By Microprocessor

By device on the other side

programmable counter interval timer pit 8254

WK 11

Programmable Counter/Interval Timer (PIT): 8254

Data bus

PIT

  • For each counter:
  • Clock Input: - ive edge
  • Gate Input: Function
  • depends on mode, e.g.
  • 1: Count, 0: No count
  • Output: Changes state
  • on terminal count

RD/WR Control

2-bit address

Chip Select

(Obtain by

Decoding

Remaining I/O

Address lines)

  • 3 Identical and separate 16-bit presettable down counters
  • Clock frequency up to 10 MHz  Binary or BCD counting
  • Each can be programmed to operate in any of 6 modes
  • Each can be preset and read under program control
  • Programmed by writing into a command register (A1A0=11)
  • Appears as 4 I/O bytes in the processor I/O space
  • (similar to the PPI 82C55)

Note similarity with

the 82C55:

3 programmable units

+ 1 Command register

the pit in the pc
The PIT in the PC
  • The timer appears in the PC at I/O ports 20H and 23H. It generates speaker beeps and generates a periodic signal at the correct repetition frequency to refresh the DRAM
general applications
General Applications

Generation of accurate time delays under software control

  • Real Time Clock
  • Event Counter: Interrupts processor when a preset number of events occur
  • Digital one-shot (A pulse of a programmable width generated in response to an event)
  • Programmable frequency clock (fout = fin/n, n determined by software)
  • Square wave generator (programmable frequency)
  • Complex waveform generation (counter output fed to a digital to analog converter- DAC)
  • Complex motor control
close up of one counter
Close-up of one Counter

Program the counters

By writing into this

Control byte (A1A0 = 11)

2-byte Count Register

(Input Latches for writing

Initial Counts from mP

Into counter)

LS

MS

16-bit Counting Element

Counter Status:

Use the Read-back

Command to latch into

Status Latch for reading

by Processor

CR and OL are

written/read one byte

at a time across the

8-bit data bus

LS

MS

Inputs & Outputs

  • 2-byte Output Latches for reading counter Parallel output (at the counter’s I/O address with the same format specified when the counter was programmed)
  • Normally follow counter count and can be read at any time.
  • A “Counter Latch Command” latches the present counter count into them. Will be frozen till read by processor
programming the counters write operations
Programming the Counters: Write Operations
  • Each counter must be programmed before it can be used
  • A counter is programmed by writing a control word (specifying the counter) into the control word register (A1A0=11), followed by an initial count into the I/O address of that counter
  • Initial counts are written into the I/O address of the counter specified, e.g. A1A0 = 01 for counter 1
  • Initial count bytes or words specified for a counter in the control word should be sent after the control word- but not necessarily immediately following it, and programming of the 3 counters can be interleaved

Counter Mode

Specify Counter

to be programmed

Counting Method:

BCD or Binary

Reading/Writing Format

Use different formats for the

Control word- see Read Operations

Counter Latch Command

Latches present count of specified

Counter to its OL. Remains frozen

until latch is read by processor

slide83
Programming the Counters: Write OperationsAll sequences below for the Control Word followed by Initial Count bytes are valid

The arrow shows

an invalid

Sequence. Why?

read operations reading a counter while it is counting three ways
READ Operations: Reading a counter while it is countingThree Ways
  • Simple READ: Does not need a special command….Procedure:
  • - Inhibit clocking by G = 0 (Disrupts future count!) to ensure reading stable levels
  • - Simply Read the counter at the proper I/O address (e.g. A1A0=10 for counter 2)
  • Issue a “Counter Latch Command” by writing the appropriate byte into the Control Word Register (A1A0 = 11), with RW1 RW0 = 00 and specifying the address of the required counter SC1 SC0.
  • When this command is executed, Present count at the counter parallel output is latched into the counter’s output latch (OL) and remains fixed until the latch is read by the processor or the counter is re-programmed. Only then it returns to follow the counter count as before. OL bytes must be read in the same format specified when the counter was last programmed

The command byte during a

“Counter latch command”

read operations reading a counter while it is counting three ways contd
READ Operations: Reading a counter while it is countingThree Ways, Contd.
  • Read Back Command
  • Written into the control word (A1A0=11)
  • To latch Status and/or Count of any
  • of the three counters
  • (Up to all 3 counters can be
  • specified simultaneously)

The command byte written during a

“Read back command”

Up to 3 Counters

Shows how the counter was programmed

Format for the Counter Status Register

(latched into the Status latch

if so specified in the Read-Back Command)

i.e. Count = 00000H

the 6 counter modes
The 6 Counter Modes

One off

Free

Running

One off

mode 0 event counter
Mode 0: Event Counter

Count down from n till terminal (null) count

  • G input = 1 always to enable counting
  • n: Initial Count Number loaded into counter after programming it by the Control Word
  • OUT goes high at terminal count, (n+1) negative clock edges after n is written into Counter Register by software

Initial Count n = 5

Written into Counter’s CR

Initial Count n = 5

Loaded into Counter

. . . Counter decrements till Terminal Count = 00000H

OUT rises high at terminal (null) count

To Processor INTR

  • Applications:
  • Interrupt Processor on:
  • Arrival of a predetermined number of events (1 0 clk transitions) = (n+1)
  • Or elapse of a time interval t = (n+1) Tclk
  • From the writing of n by software into the counter
slide88

Mode 1: Hardware Triggered One-Shot (Monostable Multivibrator- Retriggerable)

  • Gate G in this mode is used as the monostable hardware trigger
  • It allows n to be loaded into counter, which clears OUT to 0. OUT remains 0 until terminal count
  • Duration of the 0 pulse on OUT = n Tclk
  • If Gate goes high again during the OUT pulse, monostable is retriggered to extend the pulse by another duration

Initial Count n = 5

Written into Counter’s CR

Initial Count n = 5

Loaded into Counter

. . . Counter decrements till Terminal Count = 00000H

(Trigger)

OUT goes low

At loading n

OUT rises high at terminal count

Note: In this mode G needs not be

kept high for counting to be enabled

slide89

Mode 2: Divide-by-n Counter (Programmable Frequency Clock)

  • Gate G = 1 always, to enable counting
  • OUT frequency = Clock frequency/n
  • OUT Duty cycle (ON:Total) = (n-1):n  A square wave only for n = 2

(3 pulses = n)

Initial Count n = 5

Written into Counter’s CR

Initial Count n = 5

Loaded into Counter

. . . Counter decrements till Terminal Count = 00000H

Regular Period

written Into Counter

(Trigger)

1

2

OUT goes low

At n loading

n = 3

Note: In this mode G needs not be

kept high for counting to be enabled

slide90

Mode 3: Divide-by-n Counter but with a Square Wave Output:

  • Gate G = 1 always, to enable counting
  • OUT frequency = Clock frequency/n
  • OUT Duty cycle (ON:Total) = (1:2) for n even

 1:2 for n odd and large

Initial Count n = 5

Written into Counter’s CR

Initial Count n = 5

Loaded into Counter

written Into Count Register of Counter

. . . Counter decrements till Terminal Count = 00000H

written Into Counter

4

Regular Period

(Trigger)

2

2

OUT goes low

At n loading

(Fixed)

Note: In this mode G needs not be

kept high for counting to be enabled

7

4 3

slide91

Mode 4: Software Triggered Strobe Output Pulse:

  • Gate G = 1 always, to enable counting
  • OUT gives an active low strobe pulse

- Strobe pulse duration: Fixed at 1 clock interval

- Delay from writing initial count into counter (software trigger) = (n+1) Tclk

  • Useful for strobing data generated by processor into external devices, e.g. a printer
  • Note similarity between modes 0 and 4

written Into Count Register of counter

1

slide92

Mode 5: Hardware Triggered Strobe Output Pulse:

  • Gate G is used as a hardware trigger. Not needed high for counting
  • OUT gives an active low strobe pulse

- Pulse duration: 1 clock interval

- Delay from writing initial count into counter (software trigger) = (n) Tclk

  • Useful for strobing data generated by processor into external devices, e.g. a printer
  • Note similarity between modes 1 and 5

written Into Counter

slide93

Summary of G effect

In the 6 counter modes

Event Counter

Hardware triggered

One shot

Divide by N Counter

3 pairs of similar modes

Divide by N Counter

(Square Wave Output)

Software triggered

Strobe

Hardware triggered

Strobe

slide95

8254 PIT Programming Example

8 MHz Clock Frequency

G = 1 Permanently:

Enable Counters 0 and 1

  • 200 KHz non-square wave:
  • Mode 2 (requires G = 1)

f Out = f in /n

n = 8000/200 = 40d

  • 100 KHz Square Wave:
  • Mode 3 (requires G = 1)

f Out = f in /n

n = 8000/100 = 80d

Addresses:

Counter0: 700H

Counter1: 702H

Counter2: 704H

Control Word: 706H

(Even addresses)

A0 is decoded as 0

slide96

Program

;A procedure that programs the 8254 timer to function

;as illustrated in Figure 11-34

TIME PROC NEAR USES AX DX

MOV DX,706H ; address Control register

MOV AL,00110110B ; program counter 0 for mode 3

; Counter Load/Read format is ; 2 bytes (LS first)

OUT DX,AL

MOV AL,01110100B ;program counter 1 for mode 2

OUT DX,AL

MOV DX,700H ; Address counter 0

MOV AL,80 ; Load initial count 80d into counter 0

; LS byte of initial count

OUT DX,AL

MOV AL,0; ;Then MS byte of initial count

OUT DX,AL

MOV DX,702H ; Address counter 1

MOV AL,40 ; Load initial count 40d into counter 1

OUT DX,AL

MOV AL,0 ;Then MS byte of initial count

OUT DX,AL

RET

TIME ENDP

Control Word

Waveform from

Counter 0 starts

being generated here

Waveform from

Counter 1 starts

being generated here

slide97

DC Motor Speed and Direction Control

Q 1

#Q 0

Rotation in

One Direction;

e.g. clockwise

Pulse Width Modulation for Speed Control:

Q 0

#Q 1

Rotation in

Opposite Direction

  • The Q Output (#Q is the complement):
  • No net motion with duty cycle = 1:2
  • Net motion in either direction
  • With a duty cycle < or > 1:2

OFF

ON

1

0

ON

OFF

(Preset: Q 1)

(Set bistable)

1

0

1

0

Set-Reset Bistable

(Clear: Q 0)

(Reset bistable

  • We use counter 0 and Counter 1:
  • Both driven by an 8 MHz clock
  • Both are divide-by-30,720 counters (Mode 2) (output repetition rate, f
  • = 8 MHz / 30,720 = 260 Hz (motor spec requires: 60 Hz < f < 1000 Hz)
  • Bistable is cleared (Q=0) by the #CLR signal from counter 0
  • and preset (Q=1) by the #PS signal from counter 1
  • - Duty cycle is varied by controlling the timing of #PS relative to #CLR
duty cycle motor speed control
Duty Cycle Motor Speed Control

Pulse Width Modulation (Speed Control):

  • The Q Output (#Q is the complement) duty cycle
  • Controls motion:
  • No net motion with duty cycle = 1:2
  • Net motion in either direction
  • With a duty cycle < or > 1:2

OUT of

Counter 1 (mode 2)

Width = ?

OUT of

Counter 0 (mode 2)

Duty Cycle = 1:2

Count = (30,720)/2

Wait for Counter 1

to reach this count and

start Counter 0

This is done only once

and the system is left to free-run

until a different speed is required

Duty Cycle: >1:2

Count < (30,720)/2

Waiting Count

= 30720 – AH*120

Duty Cycle: < 1:2

Count > (30,720)/2

+ max

AH = 0

AH = 255

AH = 128

  • Assume 256 different speed control settings:
  • Represented by byte variable in AH
  • = 128 for no motion (1:2),
  • = 0 -127: Speed in one direction (<1:2). 0: Maximum speed in that direction
  •  = 129 – 255: Speed in the other direction direction (>1:2), 255: Maximum speed in that direction
  • Increment Count for each speed control setting = 30720/256 = 120
  • e.g. for AH = 128: Delay count = 128 x 120 = 15360 (as seen above for no net motion (2:1))

Speed

AH

0

128

255

- max

slide99

= AH x 120

= 128 x 120

From Counter 1

From Counter 0

 230 x 120

Waiting Time = 30720 – AH * 120

Approx same speed but in opposite directions

 25 x 120

slide100

;A procedure that controls the speed and direction of the motor

;in Figure 11-40.

;

;AH determines the speed and direction of the motor where

;AH is between 00H and FFH.

CNTR EQU 706H ; PIT Control Word

CNT0 EQU 700H

CNT1 EQU 702H

COUNT EQU 30720

SPEED PROC NEAR USES BX DX AX

MOV BL,AH ;calculate count corresponding to AH: AH has speed control byte (0128255)

MOV AX,120

MUL BL ; Multiply AH (speed input) by 120

MOV BX,AX ; result in AX, save in BX (BX has AH x 120)

MOV AX,COUNT

SUB AX,BX

MOV BX,AX ; Subtract from 30720, Now BX has 30720 – AH x 120 = waiting count

MOV DX,CNTR

MOV AL,00110100B ; program control word

OUT DX,AL ; for counter 0: Binary, Mode 2, 2 bytes R/W

MOV AL,01110100B ; same for counter 1

OUT DX,AL ; but do not start it yet by loading COUNT- do this after waiting time

MOV DX,CNT1 ; program counter 1 to generate the clear (#CLR) signal for Q (free-running)

MOV AX,COUNT ;

OUT DX,AL ; LS byte of 30720 first

MOV AL,AH

OUT DX,AL ; then MS byte

.REPEAT ; wait for counter 1 count to reach Waiting Count in BX

IN AL,DX ; Read LS byte of counter 1 (goes as AL)

XCHG AL,AH ; Put it in AH

IN AL,DX ; Read MS byte of counter 1 (goes as AL)

XCHG AL,AH ; swap AL and AH to put things back to order

.UNTIL BX == AX

MOV DX,CNT0 ;program counter 0

MOV AX,COUNT ; to generate a set (#PS) for Q (free-running) after that waiting

; delay by Counter 1. Note you also load COUNT as with Counter 1

OUT DX,AL ; Actual outputting LS byte then MS byte

MOV AL,AH

OUT DX,AL

RET

SPEED ENDP

For Control Reg

Always LS then MS

Counter 0 starts, free running at 260 Hz,

Repeatedly read counter 1

Until it reaches “Waiting Count”

Counter 0 starts free running at 260 Hz,

delayed by waiting count

from the start of Counter 1

the 16550 uart

WK 12

The 16550 UART
  • Universal Asynchronous Receiver Transmitter
  • Baud rates up to 1.5 M bauds (signal elements/s)
  • = Data rate (bps) for binary data
  • Compatible with Intel and other Processors
  • Includes:

- A programmable baud rate generator

- 16-byte FIFO buffers at input and output to help processor deal with data bursts

asynchronous serial data communication
Asynchronous Serial Data Communication
  • Data sent asynchronously using the format illustrated below
  • We often use one start bit and one stop bit to frame the data, which is usually 8-data bits with or without parity

Usually a byte of data

the 16550 uart functional description
The 16550 UART: Functional Description
  • Totally independent Transmitter (TX) and Receiver (RX) Sections
  • This allows communication in the following modes:

- Simplex: Only TX or RX is used (one direction all the time)

- Half Duplex: TX then RX (two directions at different times)

- Full Duplex: TX and RX simultaneously (two directions at the same time)

  • Can control a modem using six signals, e.g. #DSR (Data Set Ready) input, #DTR (Data Terminal Ready) output….

Here the UART is the data terminal and modem is the dataset.

40 pin DIP

the 16550 uart typical configuration
The 16550 UART: Typical Configuration

mP

Serial to Parallel

Or Parallel to Serial

Converters

Control

UART

Receiver

16-byte FIFO Input Buffer

PS

SIN

Serial

Comm.

Link

Transmitter

PS

16-byte FIFO Output Buffer

SOUT

Data

Memory

DMA Data Transfers:

Memory  UART Directly

Without going through the mP

the 16550 uart pin assignments
The 16550 UART: Pin Assignments

3 I/O Address bits

from Processor

(Table 11-5)

Data bus to Processor

Chip Select Inputs

(Multiple I/Ps)

Master Reset (tie to mP Reset I/P)

40 pin DIP

Serial data INput from RX

Read & Write Control inputs from mP

(with complements for versatility

Serial data OUTput to TX

Baud rate Clock output

Address Strobe (not needed with Intels)

Receiver Clock input

Crystal or

External Clock Input

Modem Interface: Inputs & Outputs

TX ready for data. Put data into

UART by DMA

Interrupt Processor

User defined outputs

RX ready with data. Take data from

UART by DMA

uarts in the pc
UARTs in the PC
  • Used to control the COM ports of the PC

- UART at I/O address 3F8-3FF: COM Port 0

- UART at I/O address 2F8-2FF: COM Port 2

programming the uart
Programming the UART

Two Stages:

a. Initialization Dialog: (Setup)

- Follows RESET

- Has two steps:

1. Program the line control register

(Set asynchronous transmission parameters: # of stop, data, and parity bits, etc.)

2. Program the baud rate generator for the required baud rate

b. Operation Dialog: (Actual Communication)

1 programming the line control register i o address a2 a1 a0 011
1. Programming the Line ControlRegisterI/O Address: A2 A1 A0 = 011

a. Initialization

Dialog

Programming

Parity Control

See next slide

Data Length = 5 bits

DL bit must be set

before you can

load the divisor

for the baud

generator

Data Length > 5 bits

See Table

on next slide

A break is a minimum

of 2 frames of 0’s

To allow programming

The baud rate generator

slide111

2. Programming the Baud rate Generator

  • Baud rate is programmed by loading a 16-bit divisor for the crystal oscillator (or external input) frequency into the I/O port addresses:
  •  {A2 A1 A0} = 000: LS Byte of divisor
  •  {A2 A1 A0} = 001: MS Byte of divisor
  • Divisor value is determined by the Oscillator frequency and the baud rate required:
  • Divisor = Oscillator frequency / (16 * Baud rate)
  • Table shows divisor values required for various baud rates for osc frequency = 18.432 MHz
slide113

;Initialization dialog for Figure 11-45

;Baud rate 9600, 7 bit data, odd parity, 1 stop bit

LINE EQU 0F3H ; A2 A1 A0 = 011 for the Line Control Register

LSB EQU 0F0H ; A2 A1 A0 = 000 for LSB of divisor

MSB EQU 0F1H ; A2 A1 A0 = 001 for MSB of divisor

FIFO EQU 0F2H ; A2 A1 A0 = 010 for the FIFO Control Register

INIT PROC NEAR

MOV AL,10001010B

OUT LINE,AL ; Enable Baud rate programming See slide 108

; program Baud 9600

; Divisor = 120d (see Table on slide 110)

MOV AL,120 ; LSB of divisor

OUT LSB,AL

MOV AL,0 ; MS Byte of divisor

OUT MSB,AL

MOV AL,00001010B ;program 7 bit data, odd

OUT LINE,AL ;parity, 1 stop bit

;(& disable baud rate programming?)

MOV AL,00000111B ;enable transmitter and receiver

OUT FIFO,AL ;by writing into the FIFO control Reg.

RET

INIT ENDP

Must write this

into FIFO Register

to enable communication

and operation dialog

programming

16550 fifo control register write
16550 FIFO Control Register (Write)

I/O Address: A2 A1 A0 = 010

1

1

1

Required to enable

actual communication

(Operation Dialog)

16550 line status register lstat

b. Operation

Dialog

Programming

16550 Line Status Register (LSTAT)

I/O Address: A2 A1 A0 = 101

Before reading data

from receiver, ensure

RX has data

[DR (bit 1) = 1]

Error status bits

Any being 1 indicates

An error

Before writing data

for transmission,

Ensure TX is ready

to take it

[TH (bit 5) = 1]

slide116

;A procedure that transmits the byte in AH serially

;via the 16650 UART

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

SEND PROC NEAR USES AX

.REPEAT ;test the TH bit (bit 5) in to see if TX is available

IN AL,LSTAT

TEST AL,20H ;20H is the mask for the TH bit

.UNTIL !ZERO?

MOV AL,AH

OUT DATA,AL ;send data to TX

RET

SEND ENDP

(LSTAT)

slide117

; Procedure receives byte from UART into AL if no comm. error

; If error detected, it load Al with ‘?’ as an alert

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

REVC PROC NEAR

.REPEAT

IN AL,LSTAT ;test DR bit

TEST AL,1

.UNTIL !ZERO?

TEST AL,0EH ;test for any error

.IF ZERO? ;no error

IN AL,DATA ;Read RX Data Register into AL

.ELSE ;any error

MOV AL,’?’ ;Put “?” in AL to indicate error

.ENDIF

RET

RECV ENDP