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Serial Communication: UART

Serial Communication: UART. Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu. Asynchronous Serial Communication -- UART. Universal asynchronous receiver/transmitter Transmit bits in a single channel simplex (one way)

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Serial Communication: UART

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  1. Serial Communication: UART Computer Science & Engineering DepartmentArizona State University Tempe, AZ 85287 Dr. Yann-Hang Leeyhlee@asu.edu

  2. Asynchronous Serial Communication -- UART • Universal asynchronous receiver/transmitter • Transmit bits in a single channel • simplex (one way) • half-duplex (one direction at a time) • full-duplex (two way) • A sequence of bits – packet or character • ASCII code – 7 bits for 128 characters (alphabet, numerical, and control) • fixed length or variable length • Start, stop, and parity bits

  3. EIA RS232 • Connection and signal characteristics • Data terminal equipment and data communication equipment • Logic '1' (marking) – -3v to -25v with respect to signal ground • Logic “0” (spacing) – +3v to +25v • Not assigned –between -3v and +3v (a transition region)

  4. RS232 (continued) • Flow control (handshaking) signals to avoid buffer overflow or lock-up. • RTS – to prepare the DCE device for accepting transmission • CTS -- to inform the DTE device that transmission may begin • DCD: data carrier detected • DSR: DCE ready • SG: system ground • DTR: DTE ready DTE FEP DB25 DCE MOD DB25 1 FG --------------- 1 FG 2 TX --------------> 2 TX 3 RX <-------------- 3 RX 4 RTS --------------> 4 RTS 5 CTS <-------------- 5 CTS 6 DSR <-------------- 6 DSR 7 SG --------------- 7 SG 8 DCD <-------------- 8 DCD 20 DTR --------------> 20 DTR

  5. Signal Format for ASCII Character • data, start, stop, and (even or odd) parity bits

  6. Null Modem Connection • When two DTEs are connected

  7. Hardware Flow Control • In RS232 • The sender (computer) sets its RTS line to signal that some information is present. • The receiver checks if there is room to receive the information and if so, it sets the CTS line to start the transfer. • In null modem connection • The RTS output signals that the device (computer) is capable of receiving information • So, CTS indicates that sending is allowed • Transmitter RTS or Receiver RTS

  8. Basic Operations • Parallel / serial conversion • Buffering (FIFO) • Clock synchronization and Data sampling • Baud rate generator • Parity generator and checking • Example: 16550

  9. Coldfire UARTs • UARTs are clocked by an external clock or by the internal bus clock • Full-duplex asynchronous/synchronous receiver/transmitter • Quadruple-buffered receiver and double-buffered transmitter • Programmable data format: • 5–8 data bits plus parity • Odd, even, no parity, or force parity • One, one-and-a-half, or two stop bits • Each serial channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode • Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • Detection of breaks originating in the middle of a character • Start/end break interrupt/status

  10. Coldfire UARTs • The DMA controller allows large blocks of data to be transferred without intervention from the CPU. • Once the DMA registers have been programmed, a transfer can be started that will relocate data from one memory location to another or write data to/from a peripheral.

  11. Coldfire UART Clock • Use external clock for synchronous operation • Use system clock for baud generation baud rate = fsys/(32*divider)

  12. Coldfire UART TX and RX FIFO • TEMP: Transmitter empty, (both the transmitter holding register and transmitter shift registers are empty). • TXRDY: The transmitter holding register is empty and ready for a character. • RXRDY: Receiver ready. One or more characters were received and are waiting in the receive buffer FIFO. • FFULL: FIFO is full.

  13. Coldfire UART Initialization Sequence

  14. Example: Loop Back Test // Reset receiver, transmitter, and mode MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_RX; MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_TX; MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_MR; // Initialize input enable control MCF_UART_UACR(channel) = 0; // Select rx and tx clock as internal MCF_UART_UCSR(channel) = 0 | MCF_UART_UCSR_RCS_SYS_CLK | MCF_UART_UCSR_TCS_SYS_CLK; // Set baud rate ubgs = (uint16)((sysclk*1000)/(baud * 32)); MCF_UART_UBG1(channel) = (uint8)((ubgs & 0xFF00) >> 8); MCF_UART_UBG2(channel) = (uint8)(ubgs & 0x00FF);

  15. Example: Loop Back Test // Set 8-bit, even parity in UMR1, no RxRTS for loopback test MCF_UART_UMR(channel) = 0 | MCF_UART_UMR_BC_8| MCF_UART_UMR_PM_EVEN; // Set 1 stop bit, and local loop back channel mode MCF_UART_UMR(channel) = 0| MCF_UART_UMR_SB_STOP_BITS_1 | MCF_UART_UMR_CM_LOCAL_LOOP; MCF_UART_UIMR(channel) = 0; // Mask all UART interrupts MCF_UART_UCR(channel) = 0 | MCF_UART_UCR_TX_ENABLED | MCF_UART_UCR_RX_ENABLED; MCF_UART_UTB(channel) = test_data; //send test data while (!(MCF_UART_USR(channel) & MCF_UART_USR_RXRDY)); test_return= MCF_UART_URB(channel); // receive a test data

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