cpre coms 583 reconfigurable computing n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
CprE / ComS 583 Reconfigurable Computing PowerPoint Presentation
Download Presentation
CprE / ComS 583 Reconfigurable Computing

Loading in 2 Seconds...

play fullscreen
1 / 21
kelsey-sanford

CprE / ComS 583 Reconfigurable Computing - PowerPoint PPT Presentation

92 Views
Download Presentation
CprE / ComS 583 Reconfigurable Computing
An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. CprE / ComS 583Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #10 – HW #2 / Projects Discussion

  2. Plaintext Ciphertext Plaintext Encryption Decryption Recap – Introduction to Cryptography • Encryption is the process of encoding a message such that its meaning is not obvious • Decryption is the reverse process, i.e., transforming an encrypted message to its original form • We denote plaintext by P and ciphertext by C • C = E(P), P = D(C) and P = D(E(P)), where E() is the encryption function (algorithm) and D() the decryption function CprE 583 – Reconfigurable Computing

  3. m || m H Compare H E D E(H(m)) Private Key Public Key Signing With Message Digests • A message digest (or hash) function is a one-way function which produces a fixed length vector of an input block x of arbitrary length • A fixed length “fingerprint” of a message • Instead of signing message, sign the message digest CprE 583 – Reconfigurable Computing

  4. 1 Gbps SHA-512 Implementation • Partial unrolling (5 rounds), pipelining • 1 Gbps on Virtex-E FPGAs • See [LieGre04A] for details CprE 583 – Reconfigurable Computing

  5. Application – Private-Key Crypto • The Advanced Encryption Standard (AES) is becoming the block cipher of choice for private-key cryptography • Implementing AES on FPGA hardware has been looked at in some depth: • Approximately 50 unique research implementations! • Various commercial cores (Actel, Helion Tech, Amphion, etc.) • Approach taken – an exploration of the decisions that lead to area/delay tradeoffs in an AES FPGA implementation • End result – pareto optimal designs in terms of throughput, latency, and area efficiency CprE 583 – Reconfigurable Computing

  6. AES-128E Algorithm Round Transformation round++ KeyExpansion 128-bit key ShiftRows MixColumns AddRoundKey SubBytes 128-bit plaintext No round = 10? Yes 128-bit ciphertext CprE 583 – Reconfigurable Computing

  7. R1 R2 R3 R4 R5 Input plaintext SubBytes ShiftRows MixColumns AddRoundKey R10 R9 R8 R7 R6 Output Ciphertext KeyExpansion Results: UF10-PP3D CprE 583 – Reconfigurable Computing

  8. Application – Random Number Generation • Cryptographic applications often require good sources of random numbers: • Key generation • Initialization vectors • Types of random number generators: • Pseudo-Random Number Generators (PRNG) – appear to be random, initialized with an externally generated sequence (deterministic) • Cryptographically Secure PRNGs (CSPRNG) – a PRNG where prediction of the next input bit given a previously-generated sequence is computationally intractable • True Random Number Generators (TRNG) – output is based on some underlying physical random process CprE 583 – Reconfigurable Computing

  9. The Method [KohGaj04A] • Make use of the clock jitter in a circuit: • Variation of the significant instants of the clock • Nondeterministic, may have many sources: • Semiconductor noise • Crosstalk • Power supply variations • Electro-magnetic fields CprE 583 – Reconfigurable Computing

  10. Overall Design CprE 583 – Reconfigurable Computing

  11. Ring Oscillators Uses Propagation Delay – 130 MHz CprE 583 – Reconfigurable Computing

  12. Sampler Circuit One of the clock signals is used to sample the other signal CprE 583 – Reconfigurable Computing

  13. Sampler Output • Clock Skew(jitter) in between two clock signals is used (e.g. sampled) to generate a totally random bit • The output clock skew: • Will never be uniform • Is not simple out-out-phase behavior CprE 583 – Reconfigurable Computing

  14. Good Speed Ratios • Ring oscillators with closely matched frequencies require that a desired speed ratio must be achieved • What factors affect this achievement? • Variation in CLB speed • 7% difference between the slowest CLB and the fastest one • Sensitive to temperature and difficult for measurement • Variation in the frequency of an oscillator with the chip temperature • Close placement • To use a large number of oscillators CprE 583 – Reconfigurable Computing

  15. CLB Speed / Temperature Variation CprE 583 – Reconfigurable Computing

  16. Summary • FPGA platforms are a popular choice for implementing cryptographic applications • High throughputs • Relatively low design cost • Algorithmic agility / upload • Many other algorithms have been implemented that we haven’t discussed today: • Public-key cryptography (e.g. RSA, ECC) • Private-key cryptography (e.g. DES, 3DES) • Cryptographic hash functions (e.g. MD5, RIPEMD) • Security issues as they pertain to using FPGAs have not been fully addressed CprE 583 – Reconfigurable Computing

  17. Project Proposals • Due Sunday, 9/30 at midnight • Purpose – to provide a background and overview of the project • Goal – allow me to understand what you are intending to do • Project topic: • Perform an in-depth exploration of some area of reconfigurable computing • Whatever topic you choose, you must include a strong experimental element in your project • Work in groups of 2+ (3 if very lofty proposal) CprE 583 – Reconfigurable Computing

  18. Some Suggested Topics • Design and implementation of X • Pick any application or application domain • Identify whatever objectives need to optimized (power, performance, area, etc.) • Design and implement X targeting an FPGA • Compare to microprocessor-based implementation • Network processing • Explore the use of an FPGA as a network processor that can support flexibility in protocol through reconfiguration • Flexibility could be with respect to optimization • Could provide additional processing to packets/connections • Implement a full-fledged FPGA-based embedded system • From block diagram to physical hardware • Examples: • Image/video processor • Digital picture frame • Digital clock (w/video) • Sound effects processor • Any old-school video game  • Voice-over-IP CprE 583 – Reconfigurable Computing

  19. Suggested Project Topics (cont.) • Prototype some microarchitectural concept using FPGA • See proceedings of MICRO/ISCA/HPCA/ASPLOS from last 5 years • Survey some recurring topic • Compare results from simulation (Simplescalar) to FPGA prototype results • Evaluation of various FPGA automation tools and methodologies • Survey 3-4 different available FPGA design tools • Pick a representative (pre-existing) benchmark set, see how they fare…how well do they work? • Analyze output designs to determine basic differences in algorithms and methodology • Anything else that interests you! CprE 583 – Reconfigurable Computing

  20. Previous Year’s Topics • Fall 2006 projects: • “FPGA Implementation of Frequency-Domain Audio Filter Bank” (2 students) • “Transparent FPGA-Based Network Analyzer” (2 students) • “FPGA-Based Library Design for Linear Algebra Applications” (2 students) • “An Improved Approach of Configuration Compression for FPGA-based Embedded Systems” (2 students) • “Analysis of Sobel Edge Detection Implementations” (1 student) • “Artificial Neural Networks on Dynamically Reconfigurable FPGAs” (3 students) • Papers and presentations for these are available upon request • We can do better! CprE 583 – Reconfigurable Computing

  21. Proposal Structure • Suggested structure [3-4 pages, IEEE conf. format] • Introduction – what is the context for this work? What problem are you trying to address? Why is it interesting/challenging? • Prior work – what is the related work? How does your work differ from these? (5-10 references) • Approach – how are you going to tackle the problem? What tools and methodologies do you intend on using? What experiments do you intend on running? • Expected results –what do you expect the outcome of your project to be? What are the deliverables? How do you intend on presenting your results? • Milestones – what is your expected progress schedule? Provide a weekly / bi-weekly basis CprE 583 – Reconfigurable Computing