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COMP 1321 Digital Infrastructure

COMP 1321 Digital Infrastructure. Richard Henson University of Worcester October 2013. Week 3: The Fetch-Execute Cycle. Explain the instruction set of a typical CPU Understand the sequential way a CPU works, using its instruction set

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COMP 1321 Digital Infrastructure

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  1. COMP 1321 Digital Infrastructure Richard Henson University of Worcester October2013

  2. Week 3: The Fetch-Execute Cycle • Explain the instruction set of a typical CPU • Understand the sequential way a CPU works, using its instruction set • Understand how registers and memory addresses are used to process a CPU instruction and store the results

  3. CPUs and the SAM • SAM is a CPU simulator • designed to allow you to watch what happens when a CPU works • CPU very, very, very fast • Processes one instruction at a time • Instructions can require several cycles

  4. What is “Processing”? • Usually calculations: • need data input • from register • from external memory • need to store output • from register • from external memory • Could also be a command without data

  5. CPU types • Most frequently used: • Intel 8086 family • Motorola (esp. 68000 family) • ARM (many mobile phones) • We’ll focus on Intel 8086 family • dates back to original IBM PC…

  6. Registers • A series of memory stores inside the CPU • usually containing one word of memory • 1, 2, 4 bytes i.e. very very small! • CPU reads/writes data very very quickly to/from the registers

  7. Registers (from last week…) 0 6 6 8 1 8 4 4 Registers: high-speed memory on the CPU chip Parking places for data on the move AX BX AX and BX registers are used for ALU operations MARR MAR is memory address register, 4 in eg. Result, 6+8=14, will go into memory cell address 4

  8. 8086 CPU family registers • 8086 chip always used a 16-bit word • SAM simulates an 8-bit word • popular for most early microcomputers • Typical 8086 registers: • general purpose data: AX, BX, CX, DX • specific use e.g. • program counter: instruction address in memory • stack pointer…

  9. Data and Addressing • A general purpose register could contain • data • A memory address that points to data • Convention: • data written as hexadecimal equivalent • e.g. 4A • memory location has square brackets • e.g. [4A]

  10. Instructions • Used to tell the CPU what to do… • MOV is for moving data around… • MOV AX, 4A – move “4A” into AX register • MOV AX, [4A] – move data contained in address 4A into AX register • Other instructions for different operations… • collectively known as an instruction set

  11. 8086 in practice • Four 16-bit General Purpose registers • each gen register split into upper byte & lower byte: lower byte upper byte AX AL AH BX BL BH CX CH CL DH DL DX

  12. Another 8086 Instruction: ADD • Takes values from two registers • Adds them together • Deposits results back in one of the registers • Which one? • the register that appears first in the instruction

  13. Fetch-Execute Cycle (Organization and Control) 1. Fetch instruction from memory 5. Write back results to registers ax <- ALU add ax , bx 4. Do any Memory Access 2. Decode the instruction and read any registers (Data cache) None needed ALU <- ax ALU <- bx 3. Do any ALU operations (execute units) ax + bx

  14. 0 1 2 3 4 Fetch-Exec : State 1 Instruction Fetch add ax , bx ax bx add AX BX 3 add ax,bx 3 1 8 7 1 9

  15. 0 1 2 3 4 Fetch-Exec : State 2 Decode, Register Operations add ax , bx ax bx add AX BX 3 add ax,bx 3 1 8 7 1 3 1 9

  16. 0 1 2 3 4 Fetch-Exec : State 3 ALU Operation add ax , bx ax bx add AX BX 3 add ax,bx 8 7 1 3 1 4 9

  17. 0 1 2 3 4 Fetch-Exec : State 4 Memory Access add ax , bx ax bx add AX BX 3 add ax,bx 8 7 1 3 1 4 9

  18. 0 1 2 3 4 Fetch-Exec : State 5 Register Write add ax , bx ax bx add BX 3 add ax,bx 4 8 7 1 3 1 4 9

  19. Fetch-Execute Cycle (Organization and Control) 1. Fetch instruction from memory 5. Write back results to registers Data into ax mov ax , [1] 4. Do any Memory Access 2. Decode the instruction and read any registers Read memory at addr ‘1’ Read the ‘1’ 3. Do any ALU operations (execute units) Put ‘1’ into MAR

  20. 0 1 2 3 4 Fetch-Exec : State 1 Instruction Fetch mov ax , [1] mov ax 1 mov ax , [1] 3 8 7 1 9

  21. 0 1 2 3 4 Fetch-Exec : State 2 Decode, Register Operations mov ax , [1] mov ax 1 mov ax , [1] 3 8 7 1 9

  22. 0 1 2 3 4 Fetch-Exec : State 3 ALU Operation mov ax , [1] mov ax 1 mov ax , [1] 3 8 7 1 1 9

  23. 0 1 2 3 4 Fetch-Exec : State 4 Memory Access mov ax , [1] mov ax 1 mov ax , [1] 3 8 8 7 1 1 9

  24. 0 1 2 3 4 Fetch-Exec : State 5 Register Write mov ax , [1] mov ax 1 mov ax , [1] 3 8 8 8 7 1 1 9

  25. 8088: Brains of the IBM PC

  26. Inside the 8088 address bus address adder External buses gen registers ALU

  27. Pentium(samefamily) 1 2 • Fetch • Decode • ALU • Mem Ops • Reg Write 3 4 5

  28. Programming a CPU CPU programming code written as assembly language Each family has its own instruction set Programming syntax will depend on the instructions & how they should be used Intel 8086 assembly language is used for CPUs that support Microsoft platforms…

  29. Example 8086 Assembly Language MOV AH,08 INT 21 MOV DL,AL MOV AH,02 INT 21 MOV AH,4C INT 21

  30. So THAT’S how it all works!now you try it on SAM2…Next week: a focus on writing programs and i/o

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