ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs

1. ECE 3430 – Introduction to Microcomputer SystemsUniversity of Colorado at Colorado Springs Lecture #19 Agenda Today: • Electrical Test and Measurement Equipment • Communications (SPI, I2C, SCI, JTAG) • Direct Memory Access (DMA) ECE 3430 – Intro to Microcomputer Systems Fall 2014

2. Test and Measurement Equipment Test Equipment in General:- In all designs, there must be a way to test the circuitry. Prototype Turn-On / Debug  Verification- In this class, we deal with debug at the system level (i.e., multiple components talking to each other): Component Component Wire orPCB (printed circuit board) RAM uC/uP A/D Wires LCD ECE 3430 – Intro to Microcomputer Systems Fall 2014

3. Test and Measurement Equipment Oscilloscopes:- This is a device that will show the analog representation of what’s going on. - Today’s oscilloscopes aredigitizing. This means they use an A/D converter to acquire the waveform and then redraw it on their screen using bits stored in memory. - The waveform information is stored and processed internally by the oscilloscope in digital format. - This allows uP/uC devices to do the waveform analysis—rather than depending on custom analog electronics. Component Component Probe Point ECE 3430 – Intro to Microcomputer Systems Fall 2014

4. Test and Measurement Equipment PC Display Oscilloscopes:- Architecture:- Time base: A clock that tells the A/D when to sample.- Trigger: Point in the data record that is defined as t=0. Triggers allow the oscilloscope to stabilize the display output. Triggers can be generated internally in the scope or provided externally via a cable. Triggers must be periodic! RAM Memory Controller A/D RAM RAM Time base Trigger ECE 3430 – Intro to Microcomputer Systems Fall 2014

5. Test and Measurement Equipment Oscilloscopes (displaying data): • Display screen is divided into a grid. • Each vertical division represents a certain amount of voltage. • Each horizontal division represents a certain amount of time. • A volts/division and time/division control allow the user to “zoom in” on different parts of the waveform. voltage time ECE 3430 – Intro to Microcomputer Systems Fall 2014

6. Test and Measurement Equipment Oscilloscope Specs: Bandwidth – The analog bandwidth of the scope. This is the fastest frequency that can get into the scope (be seen by the scope). Sample Rate – Rate at which the data is sampled. The Nyquist sampling theorem states that in order to faithfully reconstruct a signal from a series of samples, the rate at which the samples were taken must be at least twice the frequency of the highest frequency component of the original signal. All electrical signals can be decomposed into a series of sinusoids (or frequency components). In modern oscilloscopes, manufacturers usually give us at least a 4x sampling rate. The sampling rate can be changed so that if you are looking at slower frequency signals, you can achieve a longer acquisition record. ECE 3430 – Intro to Microcomputer Systems Fall 2014

7. Test and Measurement Equipment Oscilloscopes: Making a scope measurement? 1) Check that scope has enough bandwidth to measure your signal. 2) Check that the scope has a high enough sample rate and that it is set to what you need. Probes: Probes are the special connectors that attach the oscilloscope to the device under test/measurement. Probes can alter the voltage that is measured—so the oscilloscope must know what kind of probe you’re using so it can compensate for the voltage differences. Probes themselves also have a bandwidth restriction. If you are measuring signals with high frequency components, you must have a good grade probe (passive vs. active probes). ECE 3430 – Intro to Microcomputer Systems Fall 2014

8. Test and Measurement Equipment Logic Analyzers:- This is a device that will show the digital representation of what’s going on. Component Component Probe Point Display only shows visual representation of bits (0 and 1)! Analog voltage is “rounded” to 0 or 1! ECE 3430 – Intro to Microcomputer Systems Fall 2014

9. Test and Measurement Equipment Display Logic Analyzers:- Architecture:- Some useful features of a logic analyzer: 1) Search for patterns (even very complex patterns). 2) Filter out data that you don’t want to store in memory. This way you have more meaningful info displayed. 3) Analyze bus transactions (see what a CPU is executing). PC RAM Acquisition IC Memory Controller Comparator RAM RAM (Converts input data to ‘1’ or ‘0’ using “programmable” reference voltage) (latches and looks for pattern) ECE 3430 – Intro to Microcomputer Systems Fall 2014

10. Test and Measurement Equipment Logic Analyzers (triggering): • A trigger in an oscilloscope is a periodic event (such as a voltage of a periodic waveform rising above a certain threshold). • A trigger in a logic analyzer is a generic event telling the analyzer to start capturing data across all the data channels. • In modern logic analyzers, triggers can be complex situations such as: • Wait until signal number 1 goes high, then wait until signals 2-3 have gone low, and finally wait until signal 4 has gone high for at least 500 ns. • Use your imagination—virtually any combination of events is possible (at least with high grade logic analyzers). ECE 3430 – Intro to Microcomputer Systems Fall 2014

11. Test and Measurement Equipment Logic Analyzers (classic modes of operation): Logic analyzers generally operate in one of two modes: • State mode • Timing mode In state mode, an external clock is provided to the logic analyzer via a dedicated input. When this clock is pulsed, the logic analyzer samples all data on the other inputs. This is useful when trying to capture synchronous data (transactions on a bus for example). In timing mode, the logic analyzer continually gathers data on all input pins as quickly as it can until it runs out of acquisition memory. Generally driven by an internal clock. ECE 3430 – Intro to Microcomputer Systems Fall 2014

12. Test and Measurement Equipment Logic Analyzer Specs: Maximum Toggle Frequency – This tells how fast of a digital signal the logic analyzer can acquire (usually different for state and timing modes). # of Channels – Since we are only storing 1’s and 0’s, we can acquire many more signals. Today’s analyzers can simultaneously monitor hundreds of signals in the same clock domain. Memory Depth – This tells how many bits of memory per channel the analyzer can store. Today’s analyzers can capture millions of bits per channel. ECE 3430 – Intro to Microcomputer Systems Fall 2014

13. Test and Measurement Equipment Protocol Analyzers: • Digital technology is becoming increasingly serial and less parallel. • For this reason, there is less of a demand for traditional parallel logic analyzers and an increasing need for serial protocol analyzers. • A protocol analyzer is just another type of logic analyzer: specifically designed to capture a sequence of bits and decode this information into something meaningful. It is able to do this with inherent knowledge of the protocol. • Examples: PCIe, USB, RapidIo, FireWire (IEEE 1394), MIPI, HDMI, et cetera. ECE 3430 – Intro to Microcomputer Systems Fall 2014

14. Digital Communications • The MSP430 (and many other microcontrollers) support ubiquitous digital communications technologies such as: • I2C (Inter-Integrated Circuit) • SCI (Serial Communication Interface – UARTs and COM ports) • SPI (Serial Peripheral Interface) • JTAG (Joint Test Action Group) • Later called IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture • The MSP430 either has a USI (Universal Serial Interface) peripheral module or a USCI (Universal Serial Communication Interface) module that supports I2C and SPI. • JTAG is used by the lab tools to communicate with the Embedded Emulation Module (EEM). The EEM aids in debugging. • Spy-Bi-Wire is a TI-invented technology for multiplexing the 4-wire JTAG interface to use only 2 wires. ECE 3430 – Intro to Microcomputer Systems Fall 2014

15. Digital Communications Serial Communication Interface (SCI):- This is an asynchronous interface. There is no clock line. Data is transferred between a sender and receiver using a 2-wire interface (TX and RX). - The data rate (called a baud rate) is agreed upon between the two ends. - Data is transferred serially using Universal Asynchronous Receiver/Transmitters (UARTs). - A low start bit and a high stop bit are used to frame a transaction. - Sometimes more than one stop bit. - Number of data bits is configurable (usually 8). - A parity bit may be sent as well as a simple check for transmission errors. - A configuration string of “8-N-1” means 8 data bits, no parity, and 1 stop bit. MSP430 supports this with the USCI module operating in UART mode. ECE 3430 – Intro to Microcomputer Systems Fall 2014

16. Digital Communications Serial Peripheral Interface (SPI):- This is a 4-wire, synchronous protocol: MISO (master in / slave out)  A.K.A. SDO, SO MOSI (master out / slave in)  A.K.A. SDI, SI SCLK (SPI clock)  A.K.A. SCK SS (slave select)  A.K.A. CS (chip select)- The MSP430 USI and USCI modules allow simple control over this. Drop a byte or word in a control register and let the hardware transfer the data. - Flag and interrupt notification provided by hardware when transfer is complete. - Each 8 or 16-bit transaction is an exchange. - The master and one or more slaves act as a large string of shift registers. - SS (slave select) is used to select the target device. - SS (slave select) may deselect a device from the chain, make the device transparent in the chain, or be used as a mode control to drive an internal state machine (JTAG works like this). It depends on the parts involved. ECE 3430 – Intro to Microcomputer Systems Fall 2014

17. Digital Communications Serial Peripheral Interface (SPI): • SPI-compliant devices are attached in a ring. • Only one device is a master device. All others are slave devices. • Only the master is allowed to initiate a data transfer. • Each SPI data transfer is typically 8-bits or 16-bits. Multiple SPI data transfers are used to transfer more. Interface method #1 (daisy chain): Master Slave #1 Slave #2 MOSI MOSI MISO MOSI MISO SCK SS SCK SS SCK SS MISO n connected slaves… ECE 3430 – Intro to Microcomputer Systems Fall 2014

18. Digital Communications Serial Peripheral Interface (SPI): Interface method #2 (SS pulled up on master  not floating): Master Slave #1 MOSI MOSI MISO SCK SS SCK SCK Slave #2 MOSI MISO SS MISO n connected slaves… General Purpose Output 1 General Purpose Output 2 ECE 3430 – Intro to Microcomputer Systems Fall 2014

19. Digital Communications Serial Peripheral Interface (SPI): • Interface method #1: • Each SPI device is connected in one continuous chain. • All data transfers initiated by the master. • To send data to slave #2, the data must shift through slave #1 first. • For slave #1 to send “reply” data to the master, the data must go through slave #2. • Very similar to JTAG chain or, conceptually, a big shift register. • Interface method #2: • Each SPI device is connected directly to the master (not the other slaves). • All data transfers initiated by the master. • The master can send data directly to any of the slaves by asserting the SS line. • The slave can send “reply” data directly back to the master. Why would one be better than the other? ECE 3430 – Intro to Microcomputer Systems Fall 2014

20. Digital Communications Inter-Integrated Circuit (I2C): • Multi-master bus. • 2-wire, synchronous interface. • Clock and data line must be pulled to logic 1 through pull-up resistors! • Master provides clock, slaves listen. • Each device has a 7 or 10-bit address. • Data transferred most-significant bit first. • First byte represents selected slave device and direction (read or write). Usually 7-bit device address and 1-bit for R/W. • What follows then is device specific. • Every 8 bits are acknowledged by the slave pulling the SDA line low. • Framing is done by start and stop conditions. • Start condition: Falling edge of SDA while SCL is high. • Stop condition: Rising edge of SDA while SCL is high. • SMBus (System Management Bus) technology is a superset of I2C. • MSP430 USI and USCI modules support this bus type. ECE 3430 – Intro to Microcomputer Systems Fall 2014

21. Digital Communications Joint Test Action Group (JTAG), IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture: • 4-wire, synchronous interface: • TCK (clock) • TMS (mode select) • TDI/TDO (input and output) • Similar in concept to SPI—but the TMS (mode select) replaces the SS (slave select). • The TCK and TMS inputs alone can drive state transitions in all devices. • The state machine implemented in all JTAG devices is called a Test Access Port (TAP) controller. • All TAP controllers are always in the same state. • By exercising the state diagram, devices can be selected or de-selected from the chain. • Also, a number of “data registers” can be selected onto the shift-register chain by shifting a “data register selection code” (or instruction) into the instruction register. • All 1’s in an instruction register select the “bypass device” mode (single D flip flop). • Setting TMS high and pulsing TCK 5 times will always return all TAP controllers to Test-Logic-Reset. • Simple algorithm for detecting the total number of devices in the JTAG chain. ECE 3430 – Intro to Microcomputer Systems Fall 2014

22. Digital Communications Joint Test Action Group (JTAG): • All inputs and outputs can be monitored. • Signals can be controlled. • Built-In Self-Test (BIST) systems can be probed through JTAG interface. • TI’s Spy-Bi-Wire is a 2-wire version of JTAG. This is how code is downloaded to your Flash and how the debugger communicates with the MSP430. ECE 3430 – Intro to Microcomputer Systems Fall 2014

23. Digital Communications JTAG TAP Controller State Diagram: • Begin in Test-Logic-Reset. • Use TCK and TMS to drive state transitions. • Enter Shift-IR to shift in an instruction (data register selection). • Loop around to Shift-DR to read/write the values of a data register. ECE 3430 – Intro to Microcomputer Systems Fall 2014

24. Direct Memory Access (DMA) • DMA means delegating hardware outside of the central processing unit to moving (copying) data in memory from one place to another. • Since peripherals can be memory-mapped, this could mean unloading data from peripherals into RAM for example. • Basic data movement is trivial for a powerful CPU and a waste of its time. • Examples: • Moving video data from a frame buffer in RAM out to hardware memory. • Offloading a series of digital values from an A/D converter into RAM when a conversion is complete. ECE 3430 – Intro to Microcomputer Systems Fall 2014

25. Direct Memory Access (DMA) • A transfer involves a source address, a destination address, and the amount of data to move. • The source and/or destination address may be fixed. This makes sense only if the fixed source or destination is a reactive control register (hardware reacts to data written to or read from the register by advancing internal memory pointers). • Basically you write the source and destination address, specify any other parameters such as transfer block size, and tell the DMA peripheral to start. • When the transfer is complete, the DMA peripheral can notify the CPU via interrupt or simply set a flag. Most of the time, interrupts are generated to justify the DMA approach (if the CPU had to poll for completion—in most situations it might as well just move the data itself). • Some versions of the MSP430 have a DMA on-chip peripheral device. ECE 3430 – Intro to Microcomputer Systems Fall 2014

26. THAT’S ALL FOLKS! ECE 3430 – Intro to Microcomputer Systems Fall 2014